Programmable logical arrangement

Basic principle of a PLA

A programmable logic arrangement , often referred to in English-language specialist literature as a programmable logic array or PLA for short , is a form of programmable logic circuit that consists of two AND and OR matrices connected in series. A less commonly used term is Fieldprogrammable Logic Array ( FPLA ).

General

A PLA is used to produce switching networks and plants for logical functions in disjunctive form . The AND matrix represents the conjunction terms . The selection of the conjunction terms takes place within the framework of programming (mostly using a special device) by removing switching elements from the AND matrix. The disjunctive linking of the conjunction terms is done using the OR matrix. However, the technical implementation of both matrices is often done using NAND gates. In 1986, the more universal PLAs had largely displaced the PALs , which were technically older in terms of development, from the semiconductor market.

Today PLAs are rarely used and have been almost completely replaced by CPLDs . Like PLAs, CPLDs have no restrictions regarding the usability of the AND / OR matrices in the entrance area, are electrically programmable and can also be erased again, like FPGAs, can be programmed in standardized hardware programming languages ​​such as VHDL and also have a certain number of registers .

realization

Originally, an array of fuses is (engl. Fuse ), wherein during programming in accordance with the to be programmed bit - pattern , individual fuses with a high current have been blown. One of the problems with this technology was that, over time, individual fuses could “repair” themselves through crystallization processes .

With the newer antifuse technology , the PLA consists of a diode matrix in which each diode represents one bit . In contrast to fuse technology , where a conductive connection is interrupted, the diodes are connected in such a way that they normally block the current. During the programming process, certain diodes are now specifically loaded with a very high current. This destroys these diodes and creates a conductive connection.

After the “burn process” of the PLA, the written data is represented by a bit pattern of defective and functioning diodes. This data can now be read out as often as required. PLAs belong to the group of OTP components .

The number of inputs and outputs does not have to be identical. Once a module has been programmed, it can no longer be changed, which is no longer a problem in series production. During the development phase of electronic circuits, however, so-called GALs ( Generic Array Logic ) are often used, which can be erased and reprogrammed several times.

Illustrative example

Eingangssignal 1:  Anschaltknopf (an/aus)
Eingangssignal 2:  Sicherheitsschalter (an/aus)

Ausgangssignal:    Motor (an/aus)

One possible programming would be:

Wenn Anschaltknopf = an  UND  Sicherheitsschalter = an,  dann Motor = an.
Wenn Anschaltknopf = an  UND  Sicherheitsschalter = aus  ODER
wenn Anschaltknopf = aus UND  Sicherheitsschalter = an   ODER
wenn Anschaltknopf = aus UND  Sicherheitsschalter = aus, dann Motor = aus.

The motor could also be controlled with two switches in series, so that the circuit is only closed when the power button AND the safety switch are closed. In the example, however, the use of a PLA should be illustrated. In PLAs, input and output signals can now be linked to one another in a very complicated way in a very confined space.

Delimitation and special cases

In parlance, the term PLA or GAL has established itself for the area of ​​“smaller” components of programmable logic, while the terms ASIC , FPGA and CPLD have established themselves for components of “higher” complexity , depending on the type of implementation.

The following programmable logic circuits are special cases of PLAs :

• Programmable Array Logic (PAL): Only the AND array can be programmed here.
• Programmable Read-Only Memory (PROM): Only the OR array can be programmed here.

See also

• EPROM - Erasable Programmable Read Only Memory

literature

• Erwin Böhmer, Dietmar Ehrhardt, Wolfgang Oberschelp: Elements of applied electronics. 15th edition. Vieweg Verlag, Wiesbaden 2007, chapter ROMs, PROMs and PLDs. (ROM, PLD and PAL on pp. 268–269, structure and programming of GALs in the appendix, pp. 418–419).
• Hans Martin Lipp: Basics of digital technology. Oldenburg Wissenschaftsverlag, ISBN 978-3-486-25916-2 (ULA on p. 169–170; PLA on p. 172).
• A. Auer: Programmable logic IC, properties, application, programming. Hüthig Buch Verlag, Heidelberg 1990 (structure and programming of Programmable Logic Device (PLD), Generic Array Logic (GAL), Modifiable Gate Arrangement (AGA) and Logic Cell Array (LCA)).
• Edgar Gaßner, Max Reidl: TTL 7400 IC integrated circuits, data dictionary, comparison table . Section 6: FPLA field-programmable logic unit, p. "6-2" to "6-10" and p. "2-349" (Structure and precise programming of FPLAs of types 74S330J / N, 74S331J / N, 54S330J and 54S331J -with 12 inputs and 6 outputs- from Texas Instruments).
• Manfred Seifart : Digital circuits. VEB Verlag Technik Berlin, Berlin 1986, 2nd edition, ISBN 3-341-00148-4 , chapter: "Programmable logic arrangements / basic structure of a PLA", "Mode of operation of a PLA", pp. 274-278, "Design methodology for the PLA -Programmierung ", pp. 278–280 (including comparison of the structural design of PROM, PLA and PAL).

Web links

• Applet for experimenting with ROM, PLA and PAL structures. Function input by clicking in the table of values ​​or programming matrix

Individual evidence

1. ↑ Manfred Seifart: Basic structure of a PLA . In: Digital circuits . 2., through Edition Verlag Technik, Berlin 1986, ISBN 3-341-00148-4 , p. 273 .