Verilog
Verilog , standardized as IEEE 1364 , is a hardware description language that is used for modeling electronic systems. Along with VHDL, Verilog is the most widely used hardware description language worldwide.
history
Verilog HDL was originally designed as a simulation language by Phil Moorby at Gateway Design Automation in 1983/84 . The second important area of application is the synthesis of digital circuits. Gateway Design Automation was acquired by Cadence Design Systems in 1990 . Cadence now owned the rights to Verilog and the Verilog-XL logic simulator.
In parallel with Verilog HDL, the VHDL description language became more and more popular, and Cadence decided in 1995 to convert Verilog into a free standard, managed by the organization Open Verilog International (OVI, also known as Accellera). Verilog was submitted to the IEEE and adopted the same year as IEEE Standard 1364–1995 (Verilog-95).
By merging Verilog-A (modeling language for analog circuits) and Verilog to Verilog-AMS, a relatively powerful language for analog / mixed signal designs has also been available since 1998 (first version). However, no synthesis tools are available for the analog area. In 1988 Synopsys delivered a synthesis tool for Verilog for the digital sector.
Due to limitations that were criticized by users, the IEEE published an extension of the standard in 2001 under the name IEEE Standard 1364-2001, known as Verilog 2001.
In June 2002, SystemVerilog 3.0 was released, an extension for the IEEE Standard 1364-2001. With SystemVerilog it was now possible not only to describe hardware, but also to elegantly verify it. With SystemVerilog, Verilog became the first hardware description and verification language ( English Hardware Description and Verification Language , or HDVL for short ). Language extensions have also been made continuously in the last few years.
functionality
Verilog HDL allows hardware (e.g. ICs ) to be described on a higher level of abstraction than would be possible with a schematic entry program. The architecture, the behavior and lower abstraction levels at the gate level can be described.
Example of an AND gate ( and gate )
// Dies ist ein Verilog HDL Kommentar
// Deklaration der Variablen als einfache Leitung
wire result, a, b;
// Es gibt 3 Varianten, um ein (bitweises) UND-Gatter zu beschreiben
// Möglichkeit 1
assign result = a & b; // kontinuierliche Zuweisung
// Möglichkeit 2
and instanzname(result,a,b); // Instanzierung eines vorhandenen Moduls (hier ein eingebautes primitive)
// Möglichkeit 3
always@(a or b) // Verhaltensbeschreibung
//reagiert auf jede Änderung von a oder b (Bei kombinatorischer Logik)
begin
result = a & b;
end
always@(a or b) // alternative Verhaltensbeschreibung
//reagiert auf jede Änderung von a oder b (Bei kombinatorischer Logik)
begin
if (a) then result = b;
else result = 1'b0;
end
Example of a behavioral description of a flip-flop (synthesizable)
// Deklarationen
reg register_value; // als Register oder Speichervariable
wire reset, clock, set, en, datain; // als Leitung
// Flipflop mit asynchronem Rücksetzen, synchronem Setzen und synchronem Enable
always @(posedge clock or negedge reset)
begin
// Register reagiert auf positive clock-Flanke oder fallende reset-Flanke.
if (!reset) //asynchrones Rücksetzen, wenn reset = LOW
register_value <= 1'b0;
else if (set) // synchrones Setzen, wenn set = HIGH
register_value <= 1'b1;
else if (en) // synchrones Übernehmen des Wertes von datain, wenn en = HIGH
register_value <= datain;
end
In addition to the description options for hardware, Verilog HDL also offers features from other languages, e.g. B. can be used for debugging or for providing a test environment. For example, it is possible to output text messages.
module hello; // Module Deklaration mit dem Schlüsselwort "module" <name>;
initial $display (“Hallo Welt“); // Einmalig ausführen, $display ist vergleichbar mit printf in C
endmodule // Module ende Deklaration mit dem Schlüsselwort endmodule
See also
- ASIC ( Application Specific Integrated Circuit )
- CPLD ( Complex Programmable Logic Device )
- FPGA ( Field Programmable Gate Array )
- Just Hardware Definition Language
- SystemC
- SystemVerilog
- VHDL ( Very high speed integrated circuit hardware description language )
- VLSI ( Very Large Scale Integration )
- synthesis
literature
- Harald Flügel: FPGA design with Verilog . Oldenbourg, Munich 2010, ISBN 978-3-486-59234-4 .
- Bernhard Hoppe: Verilog. Modeling for synthesis and verification . Oldenbourg, Munich a. a. 2006, ISBN 3-486-58004-3 .
Web links
- Verilog tutorial at Mikrocontroller.net
- Icarus Verilog