Complex Programmable Logic Device
Complex Programmable Logic Devices ( CPLD ) represent so-called programmable logic circuits in digital technology . They are the technological successors of Programmable Array Logic (PAL) and have a simpler structure than the much more complex Field Programmable Gate Arrays (FPGAs).
construction
CPLDs essentially consist of the following elements:
Input / output blocks can be fast memories such as latches , D flip-flops or registers . In many modern PLDs , programmable outputs are available to which defined states ( active low, active high, tristate ) can be assigned. Any combinatorial link can be assigned to the AND / OR matrix as the core.
A CPLD is made up of many SPLDs (simple programmable logic devices). These are called macro cells. The individual SPLDs are in turn connected to one another via buses. The homogeneous structure enables an exact determination of the throughput times, which makes the essential difference to the FPGAs . Another, albeit not fundamentally necessary, difference is the configuration: thanks to production in EECMOS electronically erasable complementary metal oxide semiconductor , the program remains in the CPLD after configuration and does not have to be reloaded each time it is started. This configuration criterion is not an essential distinguishing feature between CPLDs and FPGAs, but it is currently not technologically possible to accommodate the much more complex FPGA structures together with EEPROM cells on a chip, as is the case with a CPLD. Reconfigurable FPGA components on the market without external memory are currently (mid-2007) so-called multi- die solutions. Several semiconductor chips, manufactured using different technologies, such as a conventional SRAM-based FPGA chip and a flash configuration chip are housed together in a chip housing. External memory is then no longer required for the FPGA.
Due to the high number of inputs / logic blocks, CPLDs are particularly suitable for solving complex, parallel, combinatorial AND / OR logic, where many inputs and outputs are required. At the same time, the number of required memories ( flip-flops ) should be low when using CPLDs, since usually only one flip-flop is available as a register for each input or output pin. Digital circuits that require many registers, such as shift registers or digital counters , can therefore only be implemented efficiently to a certain extent in CPLDs.
As the number of cells increases, the macro cells are combined with local lines to form higher-level structures such as logic array blocks , LABs. However, these names vary depending on the manufacturer.
Manufacturers are for example Xilinx , Altera , Lattice , Actel , Lucent , Cypress , Atmel or Quicklogic .
Web links
- CPLD basics at mikrocontroller.net