Sea of ​​Gates

from Wikipedia, the free encyclopedia
Structure of a microchip in sea-of-gates technology.

The English term sea-of-gates describes a technology for the design of integrated circuits . It is a further development of the gate arrays . As with a gate array, an integrated circuit (IC, microchip) or an application-specific integrated circuit can also be implemented with a sea-of-gates chip . The advantage of a sea-of-gate over a full-custom or semi-custom microchip lies in the lower investment costs .

construction

As with gate arrays, a large number of microelectronic components, mainly transistors , are housed on the so-called master , which can be connected to the desired function by the chip designer using electrical lines (thin metallic conductor tracks ). The dimensions and properties of the components are fixed and only the conductor track levels can be specified by the designer of the microchip.

Sea-of-gates differ from gate arrays in that they have a higher transistor density. The complete master is filled with transistors, which are surrounded by configurable connection pads. There are no wiring channels as with the gate array. The higher component density was made possible by the introduction of several wiring levels at the beginning of the 1990s. With more metal layers it became possible to realize the wiring above the transistors instead of next to the transistors. This meant that the dedicated routing resources of the gate arrays could be omitted and the chip area could be used for additional transistors. The sea-of-gate technology thus offers better utilization of the chip area and is therefore also suitable for regular repetitive structures such as ROMs or RAMs .

On the master there are long lines consisting of the diffusion areas for the transistors, above which gates for the NMOS and PMOS transistors are located at periodic intervals . The problem with this arrangement is the lack of isolation of adjacent transistors. Different transistors are separated from each other by so-called separation gates . To do this, the separation gate for NMOS transistors is connected to ground (0 volts) and for PMOS transistors to the supply voltage, whereby both the NMOS and PMOS transistors block.

The elements are connected with the exception of individual cases, such as B. IO cells with special functions, largely automated with the help of generator software that analyzes and implements a circuit description on the basis of a network list. On this basis, the exposure masks for the wiring levels are then created and applied to the wafers ordered by the customer.

Individual evidence

  1. ^ Naveed A. Sherwani: Algorithms for VLSI Physical Design Automation . Springer , 1998, ISBN 0-7923-8393-1 , p. 25 .
  2. ^ A b Hubert Kaeslin: Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication . Cambridge University Press , Cambridge 2008, ISBN 978-0-521-88267-5 , pp. 559 .
  3. ^ Ekbert Hering, Klaus Bressler, Jürgen Gutekunst: Electronics for engineers and scientists . Springer, Berlin 2005, ISBN 3-540-24309-7 , pp. 541 .
  4. ^ A b Hubert Kaeslin: Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication . Cambridge University Press , Cambridge 2008, ISBN 978-0-521-88267-5 , pp. 8 .