Chip design

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In microelectronics, chip design (or chip development ) refers to the process of developing a microchip from the first idea through specification and implementation in a circuit diagram and layout to the finished circuit.

Design methods

Layout for the formation of the masks in a simple CMOS operational amplifier

The problems of increasing complexity as well as cost and time pressures have led to the development of different methodologies of chip design. What all methods have in common is that masks are used for photolithography , with which production in semiconductor technology is possible. The differences between the methods are the development effort and the design flexibility.

The name of the method is often closely related to the desired product and can be classified as follows:

  • Design as a standard circuit
    • Hard-wired full design. This is the classic method that offers all the possibilities of semiconductor technology, including analog circuits. This is mainly used to manufacture mass products such as B. microprocessors , RAM modules and products with special requirements such. B. analog-to-digital converters , components of automotive electronics.
    • Mask programming. The function is defined with a design methodology as above, however the contents for integrated memories can only be defined (wired) by changing the photomasks of the last production step. Examples: ROM , microcontroller .
    • Application-specific programming. Based on a standard component, the existing logical basic elements can be connected by subsequent programming without the need for lithographic masks again. Examples: PROM , PLD , PLA , FPGA .
  • Design as an application specific integrated circuit (ASIC). Is used for highly specialized modules in mostly smaller quantities.
    • Full custom design
    • Semi-custom design

Full custom design

The development of the chip or the integrated circuit does not take place with prefabricated cells or circuit parts, but individually adapted to the requirements of the circuit to be designed. A basic distinction is made between analog and digital circuits. In the field of analog circuit technology, the full custom design is used almost exclusively. You have the option of connecting and dimensioning each individual transistor as required for the circuit to function. In the field of digital circuit technology, the semi-custom design is often used. However, this usually severely restricts the design, since it essentially uses static logic. If, on the other hand, you want to use other logic techniques such as dynamic logic, you can fall back on the more flexible full-custom design.

The full custom design is much more time consuming because it is not as highly automated as the semi custom design. However, it offers the possibility of optimizing the circuit in terms of power consumption, speed and the required chip area. Due to the great freedom in the design as well as in the execution of the layout, there is enormous potential for optimization.

For the full custom design, the semiconductor manufacturer provides the developer with so-called design kits. These are software libraries for the design tool used in each case, which offer the developer a number of primitive components (transistors, resistors, etc.) with the associated software models for circuit simulation, obtained from circuits made from measurement data.

The layout of a full custom draft is generated manually. The developer can determine and optimize the geometries of the individual transistors and the metal lines. Production restrictions in the form of geometric and electrical rules ( design rules ) must be adhered to.

Semi-custom design

In the case of semi-custom designs , the developer's freedoms are further restricted. However, this makes the development process easier, as more and more prefabricated elements are used.

Gate arrays or sea-of-gates have lost some of their importance . Both are half-finished building blocks with the transistors already in place. The logical elements are created by defining the wiring levels (metal layers) only with the appropriate photo masks. This can in principle save costs. However, the design process is limited by limited space for wiring. In the case of gate arrays in particular, in contrast to sea-of-gates, only certain areas (wiring channels) are permitted for connections. Furthermore, the driver strengths of the gates are not variable enough. The resulting disadvantages are: High power consumption and low functional density and the resulting high unit costs.

The design with standard cells is widespread . Standard cells are pre-designed elements from simple gates to flip-flops to RAM or processors . Analog blocks such as analog-digital converters are also possible. The cells can be freely placed in the layout, but have known electrical and geometric parameters. These parameters are stored in so-called libraries and are called up by the development tools. In the layout, the circuit is created by graphically lining up and connecting the standard cells. This makes the development process much easier compared to the full custom design, because a large part of the circuit simulation can be done on a logical level. With high quantities (> 100,000), the semi-custom design is the best compromise between the effectiveness of the chip design and the cost / quality of the resulting component.

For smaller quantities and complex functions, FPGAs are ideal . The design methodology has increasingly approached that of semi-custom design with increasing complexity. In contrast to this, the logical elements of the FPGA are already present on the chip and are only connected through temporary or permanent programming ( burning ). Pre-produced integrated circuits are used that have been designed as a standard circuit . A significant saving in time and costs results from the fact that the designed function "in the field", i. H. can be applied to the module by the user in a few minutes. However, the disadvantages are the sometimes very high costs, large structural shapes and the power consumption of these modules.

Design process ("design flow")

All complex digital integrated circuits are roughly developed according to the following scheme, which relies heavily on design automation tools :

  1. Specification (definition of the function in words and pictures)
  2. Description and validation at behavior level (input and simulation, for example in C / C ++ or MATLAB )
  3. Description and validation at RTL level (input and simulation in a hardware description language , see below)
  4. Synthesis (generation of gates from the RTL description)
  5. Validation at the gate level (simulation or formal verification)

The core of the modern design process is the description of the function on a higher level of abstraction called RTL (Register Transfer Level) . Here complex functions can be entered in a hardware description language (similar to a programming language ) (e.g. addition, multiplication) and the overall function of the entered RTL description can be simulated on the computer . VHDL or Verilog are mostly used as hardware description languages . A graphical input of the circuit diagram on RTL or gate level is possible, but usually not practical for larger circuits.

The RTL description is then converted into a tag description, the so-called network list , using a synthesis tool that works similarly to a compiler . This netlist can be simulated again to check the result, since it usually uses the same VHDL or Verilog syntax.

In contrast to this, the synthesis at the behavior level and the validation at the specification level are generally not automated at present (2006).

The following steps are still necessary to prepare for production:

In the case of FPGAs, the layout is not used to produce photomasks (as is the case with semi or full custom designs), but rather to produce the programming of the connections. The steps for Design Rule Check (DRC) and Tape-Out are no longer necessary.

The clock frequency is limited by the addition of the signal propagation times through the switching elements and the wiring. If modern VLSI manufacturing processes with structure sizes of 130 nm ( deep submicron ) or smaller are used, the influence of the connections on the signal propagation times increases. This has a reducing effect on the achievable clock frequency with which the block can work correctly. The results of the layout are therefore linked back to the function, which is predictable, but still requires further design cycles if the target is missed.

The runtimes of the gates and the wiring are added and displayed using "static timing analysis". The critical path is thereby determined. This represents the longest possible path that a signal can take in the circuit during a clock period and thus determines the maximum operating frequency of the entire circuit. Manufacturing tolerances and temperature effects must be taken into account. Today's designs scale down the clock rates in the system with increasing distance from the core and / or split the semiconductor into individual logical processing units, which then only perform their operations in a relatively small area but at a high frequency and synchronously.

The finished geometry data are transferred to production, where they are used to manufacture the photographic masks. The process is known as tape-out because magnetic tapes were used for this in the past . Compliance with all design rules is important so that the yield ( yield ) of functional components in the factory is as high as possible.

See also

literature

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