Structure size
The structure size or structure width (process size; see also: Minimum feature size) is a size specification used in semiconductor technology , microelectronics and nanoelectronics and describes the smallest realized (typically also equal to the minimum possible) edge length of the determining plotter -Unit. It is therefore the mask dimension , i.e. the target dimension. The dimensions of the structures produced in this way are generally somewhat smaller than the plotter unit used for the mask due to underexposure and diffusion .
The smallest structures produced on a semiconductor substrate are usually the gate length of a metal-insulator-semiconductor field effect transistor (MISFET). In this context, it is often equated with the structure size of a manufacturing process or a technology, the so-called technology node , if the term is used to refer to the entire manufacturing process geared to this structure size. However, since the smallest structure widths within a technology node can fluctuate by several percent depending on the product, this relationship is incorrect.
The term is also used in the field of digital, optical storage media, mostly for the dimensions of the lands and pits of optical storage media such as CD , DVD and Blu-ray Disc . The term is also used in nanotechnology , which deals with structures up to 100 nm in a physical-technical context .
meaning
The opened chip housing allows a view of the actual semiconductor chip
Important properties of integrated circuits correlate with the structure size used. The most important are:
- Packing density of the transistors: increases quadratically with decreasing structure size
- Compactness of a unit cell of the IC: In addition to the downsizing of the structures, the unit cells themselves have also become smaller. A DRAM cell in 1990 consisted of two transistors and took up about 50 F 2 of area; H. 200 µm² with a structure size of 2 µm. Nowadays it consists of a transistor and takes up 6 F 2 area, which corresponds to approx. 144–128 nm² with a structure size of 22 nm.
- Operating voltage: falls with decreasing structure size
- Maximum switching frequency: increases with decreasing structure size
- Power loss per gate and switching process: falls with decreasing structure size
- Robustness regarding ionizing radiation : falls with decreasing structure size
- Long-term constancy of properties through electromigration : falls with decreasing structure size
Together with the increase in wafer size in semiconductor production, the reduction in the structure size forms the two key points for reducing production costs, increasing the performance and speed of semiconductor components.
The structure size is an important parameter that is determined centrally by the semiconductor process used ( CMOS , NMOS , TTL, etc.) and the smallest or selected transistor design available for it. Here, both the material properties of the carrier, usually a are silicon - wafers , and the doping , as well as the used lithographic technique and so that the necessary manufacturing parameters such as air quality, and the like up to the current availability of factory capacity important. As a rule, conclusions can also be drawn from this about the price of such production services.
Last but not least, the structure size determines how many transistors fit on a wafer and thus also how many individual semiconductors can typically be obtained from it. Together with the logical design of the semiconductor, this results in a number of chips per wafer, which has a significant impact on the chip area and thus on the price. For example, due to the technology used, NOR flashes have lower storage capacities than NAND flashes with the same structure size , since their memory cells require more transistors and thus space on the die.
So-called die -shrinks are about replacing the structure size with a smaller one while maintaining the semiconductor functionality. One and the same functional design can thus be produced in several different structural sizes. The smaller structures often have a lower power loss in the idle state and during switching, corresponding to their transistor technology, so that the maximum clock rate typically achievable for semiconductors is usually higher for smaller structures. On the other hand, if the die size is retained, there are options for expanding scalable units, e.g. B. the cache of a processor .
In the case of smaller structures, the respective manufacturer must first take a few steps to optimize the process in order to achieve the yields that were usual up to then . Accordingly, switching to a technology with a smaller structure always entails costs and risks. It is of course attempted to keep this as low as possible in advance through suitable research and trials in order to achieve economic efficiency as early as possible.
history
Structure sizes have traditionally been given in micrometers . This was maintained for a long time in the submicrometer range, structure sizes were given as decimal fractions beginning with zero. The last time this was done at 0.14 µm. From 130 nm onwards, nanometers were used to give a clearer overview.
| Surname | Manufacturer | year | Technology features and innovations | node |
|---|---|---|---|---|
| 4004 processor | Intel | 1971 | PMOS | 10 µm |
| NMOS logic | 6 µm | |||
| HMOS semiconductors | 1.5 µm | |||
| i386DX | Intel | 1984 | 1.5 µm | |
| i486DX2 -66 with P24 core | Intel | 1992 | 0.8 µm | |
| Pentium P5 | Intel | 1993 | BiCMOS | 0.8 µm |
| Pentium P55C | Intel | 1997 | CMOS | 0.35 µm |
| Athlon (K7) | AMD | 1999 | 0.25 ... 0.18 µm | |
| VIA C3 (C5B revision) | VIA | 2001 | 0.15 µm | |
| 256 Mbit DRAM memory chip | Infineon | 2002 | 0.14 µm | |
| Storm-1 ( DSP ) | SPI | 130 nm | ||
| NEC and TSMC | 2001 | 100 nm | ||
| 2007 | 65 nm | |||
| Intel Core 2 Duo | Intel | 2007 | 45 nm | |
| XTREME ( Jenoptik and Ushio , funded by Intel) | around 2009 |
Basic research optics for EUV (13.5 nm) | initially: <40 nm 2009: 32 nm later: 13.5 nm |
|
| Memory with 45 GB / cm 2 | Tokyo University | 2004 | Optical storage | 35 nm |
|
Intel Core i3 / i5 / i7 ( Sandy Bridge in planar technology ) |
Intel | 2010 | 32 nm | |
| WITH | 2008 | Lithography technique | 25 nm | |
| NAND flash memory | Intel, Micron | 2010 | 25 nm | |
|
Intel Core i3 / i5 / i7 ( Ivy Bridge in FinFET technology) |
Intel | 2012 | 22 nm | |
| NAND flash memory | Toshiba | 2013 | 19 nm | |
| Intel Skylake microarchitecture | Intel | 2015 | FinFET | 14 nm |
| AMD Ryzen 3000 (ZEN2) | AMD at TSMC | 2019 | 7 nm | |
| 5G modem (Fusion Platform) | Qualcomm at (Samsung?) | 2019 | 10 nm | |
| Snapdragon 8150 (Fusion Platform) | Qualcomm at TSMC | 2019 | 7 nm | |
| Prodigy | Tachyum at (TMSC)? | 2020? | 7 nm |
Web links
- The race for new lithography techniques intensifies , heise-Verlag, 2001: Report on the SPIE Microlithography conference with forecasts of the expected development - was overtaken by the realities in 2007.
- Sematech puts research center for EUV lithography lacquers into operation , heise-Verlag, 2006: lacquer development for structure sizes up to 13.5 nm; Intel EUV series production planned for 2009
Individual evidence
- ↑ International Technology Roadmap for Semiconductors 2013. Process Integration, Devices and Structures . 2013, p. 18 ( PDF [accessed September 21, 2014]).
- ↑ S. Narasimha et al .: 22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL . In: Electron Devices Meeting (IEDM), 2012 IEEE International . 2012, p. 3.3.1-3.3.4 , doi : 10.1109 / IEDM.2012.6478971 .
- ^ Infineon Technologies in Dresden. (PDF) Retrieved September 6, 2014 .
- ↑ Japanese Superdisk stores 45 GB / cm2. Retrieved September 6, 2014 .
- ↑ Christof Windeck: MIT researchers show lithography technology for 25 nm structures . On: Heise Online. July 11, 2008 (news item)
- ↑ Intel, Micron Introduce 25-Nanometer NAND - The Smallest, Most Advanced Process Technology in the Semiconductor Industry . Intel News Release, February 1, 2010, accessed July 1, 2010.
- ↑ Toshiba mass produces 19nm NAND modules up to 128GByte . Toshiba News Release, October 31, 2013, accessed July 17, 2014.
- ↑ Qualcomm announces 7 nm Snapdragon with 5G
- ↑ Qualcomm announces 7 nm Snapdragon with 5G
- ↑ Small supercomputer chip should beat Intel's Xeons