NAND flash
NAND flash refers to a type of flash memory that is manufactured using what is known as NAND technology . In this case, the individual memory cells ( floating gate transistors or charge trapping memory cells ) are connected in series like a NAND gate .
There are four producers of such chips: Samsung (" Samsung Semiconductor " division), Toshiba , IM Flash Technologies (a joint venture between Micron Technology and Intel ) and Hynix in cooperation with Numonyx . The leading manufacturer is the Korean company Samsung , followed by Toshiba , which together produce the majority of all chips.
construction
The space required for a flash memory cell in the NAND-art is according to Toshiba only about 2 / 5 of the surface for a memory cell in NOR technique is required.
NAND flashes are basically page and block-oriented. A page consists of a summary of at least 512 bytes , but this has been increased in the course of the miniaturization of the transistors and the associated increase in storage density to 4096 bytes to 8192 bytes. Several pages are grouped into a block . The size of the blocks was 16 kB for smaller memory sizes and has meanwhile grown to 128 pages (512 kB with 4 kB page size) to 256 pages (2048 kB with 8 kB page size) for larger memory modules.
Pages can only be written to once; further write operations are only possible after a renewed deletion. Due to the grouping, however, a page can only be deleted by deleting the block in which it is located. As is usual with flash memories, the bits in the bytes can only be toggled from 1 to 0. The opposite way can only be achieved via a deletion process.
With NAND flashes, it is common that defective blocks, or bad blocks , are already present at the time of delivery . These are already detected by the manufacturer using special tests and marked as defective. Later they have to be taken into account by the driver software. Most NAND flash manufacturers guarantee that the first block of a memory module is error-free for a certain number of write operations. This enables the robust storage of important, permanently changing initial data, as well as the "bad block table".
With NAND flash memories, each page has a permanently assigned spare page . This was 16 bytes long for smaller modules and 64 bytes for larger modules. Bad block markings are stored in this by the manufacturer or, in the case of error-free blocks, correction data for a forward error correction (FEC) in order to be able to correct possible read errors. The spare pages are permanently linked to the user data pages: If a page, i. H. a block, deleted, the associated spare pages are also deleted. In practice, this means that blocks marked as defective may not be deleted (formatted) under any circumstances, as this would cause the error information about bad blocks to be lost. For this reason, NAND flash modules cannot be completely deleted by means of a command, but must be deleted block by block in individual steps, with the exception of the blocks marked as defective.
The initial bad blocks are determined by the manufacturer as part of extreme tests, such as extreme temperatures and variable access speeds in the limit range. Under normal conditions of use, such as at room temperature , these bad blocks do not have to work incorrectly.
In the case of NAND flashes, bit errors can also occur during operation , which must be recognized and dealt with using suitable error correction methods. Blocks with such runtime errors may have to be added to the list of bad blocks by the NAND flash controller or the software driver system. The part that is responsible for managing the bad blocks is called the Bad Block Management System .
Types of NAND memory
In a NAND flash cell, data can be stored with a different number of voltage levels as part of the floating gate . With two different voltage levels per cell, one bit can be stored per cell, these NAND cells are also known as SLC memory cells. If four different voltage levels are used, two bits can be stored per cell, as is the case with MLC memory cells . With eight voltage levels, three bits can be stored per NAND cell, called TLC memory cells ; Memory cells with 16 levels, suitable for four bits, are called QLC memory cells.
The advantage of the SLC memory cells is a higher number of write / read cycles and greater robustness, since only two voltage values have to be distinguished during the readout process.
The advantage of the MLC and especially the TLC and QLC memory cells is a more efficient use of the chip area and higher storage density. Disadvantages of these memory cell types are the longer access times and the reduced number of possible write / read cycles before failure. This reduction follows from the fact that the use of four or more voltage levels makes it more difficult to differentiate between the individual voltages and is subject to greater error probabilities.
Due to increasing problems with the structure reduction, 3D-V-NAND cells have been increasingly used since 2013. In contrast to conventional planar technology , the transistors are now vertical to the chip surface and are also arranged in several levels (see also charge trapping memory ). In competition with this, Intel and Micron have also developed the 3D XPoint storage technology.
interface
Access to NAND memories usually takes place via a multiplexed address / data bus with a width of 8 bits . The protocol used is command-based. Due to the bus interface used, a relatively large amount of software is required for control or, in hardware as the IP core , corresponding NAND flash controllers are required for access control.
The boot a system with code from a NAND memory is only possible with additional hardware in the form of a NAND flash controller. A conventional processor with an address / data bus cannot address these memories directly. With NOR flashes , however, this is possible, firmware is therefore usually stored in NOR memories.
Areas of application
NAND flashes are mainly suitable for large amounts of memory; They are used in USB flash drives , flash - memory cards (eg. CF - and SD cards), SSDs , and in virtually all MP3 players .
advantages
- Low price per megabyte
- High writing and reading speeds for large amounts of data
- Lower power consumption when writing
- NAND flashes are available with high storage capacities
- The small number of signal lines required enables cost-effective (hardware) coupling to controller systems
- The command-based bus interface enables chips with a larger storage capacity to be used without changing the circuit design
disadvantage
- Compared to NOR memories , a certain amount of software is required to control NAND memories correctly
- Due to the type of access used, NAND memories cannot be used directly as program memory for microcontrollers (these require a linearly addressable memory with random access)
- A glue logic is required to connect to conventional controller systems.
- 100,000 to 1,000,000 write-erase cycles per cell with SLC , after which the memory cell can no longer be used.
- 3,000 to 10,000 write-erase cycles per cell with MLC , after which the memory cell can no longer be used.
- approx. 1000 write-erase cycles per cell with TLC , after which the memory cell can no longer be used.
Manufacturer
| Manufacturer | Market share Q1 2016 | Market share Q2 2016 | Market share Q3 2016 | Market share Q4 2016 |
|---|---|---|---|---|
| Samsung | 34.2% | 36.3% | 36.6% | 37.1% |
| Toshiba | 23.6% | 20.1% | 19.8% | 18.3% |
| Western Digital ( SanDisk ) | 14.8% | 16.1% | 17.1% | 17.7% |
| Micron Technology | 13.0% | 10.6% | 9.8% | 10.6% |
| SK Hynix | 7.7% | 10.3% | 10.4% | 9.6% |
| Intel | 6.7% | 6.5% | 6.3% | 6.8% |
Individual evidence
- ↑ heise online: Strong growth in sales for DRAM and NAND flash memory chips. In: heise online. February 3, 2010, accessed June 15, 2014 .
- ↑ Anand Lal Shimpi: Intel & Micron Announce 25 nm NAND Flash Production, SSDs to get Bigger / Cheaper in Q4. January 30, 2010, accessed June 15, 2014 .
- ↑ STMicroelectronics (Ed.): Bad block management in Single Level Cell NAND Flash memories . Application Note AN1819, 2007 ( PDF - company publication , English).
- ↑ Micron: NAND Flash Controller via Xilinx Spartan-3 FPGA, Application Note TN-29-06 . 2005 ( PDF company publication, English).