Floating gate transistor

A floating gate transistor is a special transistor that is used in non-volatile memories for permanent information storage. It was developed in 1967 by Dawon Kahng and Simon Min Sze at Bell Laboratories and was the elementary storage element in integrated circuits in flash memories , floating gate PROMs , EPROMs and EEPROMs until the early 2000s .

Floating gate transistors in flash memories, especially NAND flash , are increasingly being replaced by charge trap flash (CTF). By avoiding interference effects, which are primarily caused by floating gate transistors in close proximity, smaller structure sizes and higher storage densities per chip area can be implemented in CTFs than with floating gates.

General

Section through an FGMOS transistor

Circuit symbol of an FGMOS with a floating gate (thick line) and three control gates V _1,2,3

Floating gate transistors, also referred to as FGMOS for short , belong to the group of field effect transistors with insulated gate (IGFETs) and are usually made from the semiconductor material silicon . In addition to one or occasionally several control electrodes (in Figure V ), it contains a "floating gate" (dt., 'Unconnected control electrode') that is electrically isolated. A certain amount of electrical charge can be permanently stored on this floating gate , which leads to a shift in the threshold voltage ( V _th ) of the transistor. As with conventional IGFETs, the source ( S ) and drain ( D ) connections are used to read the information , while the control connections are also required for writing. The bulk connection (B) is usually connected to ground potential .

The introduction or removal of the electrical charge ( electrons ) in the context of the writing process on the electrically by z. Floating gate insulated from silicon dioxide, for example, takes place through the quantum mechanical tunnel effect or through the injection of hot charge carriers ( hot-carrier injection ) from the source or drain connection, with the aid of a control connection ( control gate ). A significantly higher electrical voltage is required for the programming process than for normal reading mode (e.g. 10 V versus 3.3 V).

If there is no charge on the floating gate, the drain-source path is not affected and the transistor behaves like a normal MOSFET of the same type. For a typical FGFET of the enhancement n-channel MOSFET type , this means that the transistor is non-conductive at a gate voltage of 0 V and conductive when the threshold voltage is exceeded. However, a charge applied to the floating gate shifts the threshold voltage of the transistor. The introduction of electrons (negative charges) onto the floating gate of these transistors increases the threshold voltage. If the transistor is now controlled normally when reading out, the drain-source path of the transistor remains in a high-resistance state, that is, the transistor is non-conductive, it blocks.

With these two states, the information of a bit can be stored permanently in the simplest case . Depending on the memory technology, the transistor comprises one (with the SLC memory cell ) or several floating gates (with the MLC memory cell ). In the case of MLC memory cells, more than one bit of information can be stored in a transistor by graduating the amount of charge, which increases the storage density. Common values are two bits per floating gate transistor with four different charge levels.

State table of a floating gate transistor
process	Gate voltage	Source voltage	FG charge	Threshold voltage	transistor	Drain voltage	logic level
Read	> V _th (ex .: 3.3 V)	GND	uncharged	normal	directs	> GND	0
Read	> V _th (ex .: 3.3 V)	GND	negatively charged	elevated	locks	> GND	1
Write	> 10 V	GND	loading	increases		> 10 V	on 1
Clear	GND	GND	discharging	falls		> 10 V	to 0
resting	floating	no matter	unchanged	unchanged	locks	no matter	unchanged

Applications

The primary area of application of these transistors is in the area of digital, non-volatile memory such as USB mass storage devices or SD memory cards . With a storage capacity of 4 GB, almost 35 billion floating gate transistors are required. At high storage densities, the floating gate transistor cells are replaced by charge trap flash cells.

In 1989, as part of a research project, Intel developed a non-volatile memory cell ( ETANN ) based on FGMOS for the storage of analog values in the context of artificial neural networks .

Individual evidence

↑ D. Kahng, SM Sze: A floating gate and its application to memory devices. In: The Bell System Technical Journal. 46, No. 4, 1967, pp. 1288-1295.
↑ Betty Prince: Evolution of Flash Memories: Nitride Storage and Silicon Nanocrystal , 2006, CMOSET Conference Proceedings
↑ A. Kolodny, ST K, Nieh, B. Eitan, J. Shappir: Analysis and modeling of floating-gate EEPROM cells . In: IEEE Transactions on Electron Devices . tape 33 , no. 6 , 1986, pp. 835-844 , doi : 10.1109 / T-ED.1986.22576 .
↑ M. Holler, S. Tam, H. Castro, R. Benson: An electrically trainable artificial neural network with 10240 'floating gate' synapses. In: Proceeding of the International Joint Conference on Neural Networks, Washington, DC Volume II, 1989, pp. 191-196.

[1] D. Kahng, SM Sze: A floating gate and its application to memory devices. In: The Bell System Technical Journal. 46, No. 4, 1967, pp. 1288-1295.

[2] Betty Prince: Evolution of Flash Memories: Nitride Storage and Silicon Nanocrystal , 2006, CMOSET Conference Proceedings

[3] A. Kolodny, ST K, Nieh, B. Eitan, J. Shappir: Analysis and modeling of floating-gate EEPROM cells . In: IEEE Transactions on Electron Devices . tape 33 , no. 6 , 1986, pp. 835-844 , doi : 10.1109 / T-ED.1986.22576 .

[4] M. Holler, S. Tam, H. Castro, R. Benson: An electrically trainable artificial neural network with 10240 'floating gate' synapses. In: Proceeding of the International Joint Conference on Neural Networks, Washington, DC Volume II, 1989, pp. 191-196.