MLC memory cell

MLC memory cells ( MLC short for English multi-level cell ) are memory cells , in which more than one bit is stored per cell.

In order to make this possible, the amount of charge stored in a memory cell is dosed more finely and also evaluated more precisely when reading out in order to distinguish more than two possible states and to be able to store more than one bit. Memory with only one bit per cell is called a single-level cell ( SLC ).

The storage of several bits per memory cell has the disadvantage that the reading and writing speed is generally lower. The cells react much more sensitively to charge losses. Low charge losses of 10 percent, which do not play a role in SLCs, cause bit errors in cells with 8 possible states.

The same error correction procedures are used as in SLCs, but with a higher contingent of correction data, which again reduces the gain in capacity somewhat. As a rule, BCH codes (Bose-Chaudhuri-Hocquenghem codes) are used here.

Flash memory

The technology is mainly used in NAND flash memories, in which several bits - as of 2009 up to four ( quad level cell, also quadruple level cell ) - can be stored per memory cell, which consists of a MOSFET with floating gate . This increases the storage density. Since the advent of memory cells that can store three bits per cell ( TLC memory cells ), the term MLC memory cell is often incorrectly used synonymously for 2-bit memory cells.

Since MLC memories require less chip area with the same storage capacity, this technology is significantly cheaper than SLC memories and is mainly used for read-intensive memory requirements. In the case of products based on flash memories (e.g. USB sticks ), the abbreviations SLC or MLC in the product name can indicate the use of SLC or MLC.

background

In many memory modules, a bit is stored in each memory cell, e.g. B. in DRAMs by storing one of two possible states in the cell. A logical 0 is assigned to one state and a logical 1 to a second state. In the DRAM, a voltage of 0 V in the cell corresponds to the logical 0, and a voltage equal to the voltage VBLH ( voltage bit line high ) corresponds to the logical 1.

With different memory technologies it is possible to differentiate between more than two states of the memory cell and to assign more than one bit accordingly. So far, this has mainly been used for flash memories , but research is also being carried out on this topic for other types of memory, such as PCRAM .

Advantages and disadvantages

The main advantage of multi-level storage is the higher storage density, since more than one bit per cell is stored here. In this way, twice (or an even higher) amount of information can be stored on the same chip area than in a memory with single-level storage. In the case of semiconductor memories in particular, this offers considerable cost advantages, since the chip area required is a significant cost factor in production.

The disadvantage of multi-level storage is that, on the one hand, the evaluation of the memory content takes place more slowly - since the distance to the threshold value is smaller - and must be carried out with more complex circuits . Due to the shorter distance to the threshold value, the susceptibility to errors is also greater, since compared to single-level storage, smaller changes in the memory state are sufficient to fall into an adjacent state and thus change one or more bits. Compared to single-level storage, more complex error correction procedures are required to secure the information content of the data; BCH codes are generally used in flash memories . This achieves comparable reliability at the system level.

Examples of nominal and threshold values of the resistance for the storage of bit patterns in SLC and MLC cells
MLC cell			SLC cell
Face value	threshold value	Binary value	Face value	threshold value	Binary value
10 kΩ		00	10 kΩ		0
10 kΩ	32 kΩ	00
100 kΩ	32 kΩ	01
100 kΩ	320 kΩ	01		320 kΩ
1 MΩ	320 kΩ	10	10 MΩ	320 kΩ	1
1 MΩ	3.2 MΩ	10
10 MΩ	3.2 MΩ	11
10 MΩ		11

example

In PCRAM , a memory cell can assume resistance values in a wide range, e.g. B. from 10 kΩ to 10 MΩ. This could be used to define the following assignments to bit values and the threshold values between the states, so that several bits are stored per cell (see table).

Individual evidence

↑ Four bits per flash memory cell
↑ cf. Rino Micheloni, Alessia Marelli, Kam Eshghi: Inside Solid State Drives (SSDs) . Springer, 2012, ISBN 978-94-007-5146-0 , pp. 60 ff . ( limited preview in Google Book search).
↑ Google test finds all SSDs are created equal, in some ways. Tests puncture the myth of SLC durability. Network World, March 2, 2016, accessed March 4, 2016 .
↑ Schroeder, Lagisetty, Merchant: Flash Reliability in Production: The Expected and the Unexpected. (PDF) USENIX, February 22, 2016, accessed on March 4, 2016 (English).

[1] Four bits per flash memory cell

[2] . Rino Micheloni, Alessia Marelli, Kam Eshghi: Inside Solid State Drives (SSDs) . Springer, 2012, ISBN 978-94-007-5146-0 , pp. 60 ff . ( limited preview in Google Book search).

[3] Google test finds all SSDs are created equal, in some ways. Tests puncture the myth of SLC durability. Network World, March 2, 2016, accessed March 4, 2016 .

[4] Schroeder, Lagisetty, Merchant: Flash Reliability in Production: The Expected and the Unexpected. (PDF) USENIX, February 22, 2016, accessed on March 4, 2016 (English).