TLC memory cell
TLC memory cell ( TLC short for English triple-level cell ) are memory cells of the type NAND flash , the three bits (in English in this context as level can store called) per memory cell.
Strictly speaking, TLC memory cells belong to the group of MLC memory cells ( MLC short for multi-level cell , more than 1 bit per cell). In most of the publications in which the new TLC memories are compared with SLC and existing MLC memories, however, the MLC memory cell is basically assumed to be a 2-bit memory cell (also called 2-bit MLC memory cell).
The storage of more than two states in the cell is achieved by distinguishing between different charge levels of the floating gate when writing and reading out the floating gate transistor 8 (instead of just 2 or 4). This makes it possible to accommodate more data in the same number of memory cells, which means that the technical effort for TLC chips can be lower than for SLC and 2-bit MLC chips. However, the exact application and reliable (analog) readout of the charge as well as the testing become more complex. With increasing bit density memory cells, however, simultaneously increases the risk of failure of a cell due to increasing bit error rate (engl. Bit error rate , BER). In addition, methods such as error correction are considerably more difficult to implement than with SLC or 2-bit MLC memory cells. This means that the service life of TLC memory cells is significantly shorter than that of SLC and 2-bit MLC cells.
Individual evidence
- ↑ Rino Micheloni, Alessia Marelli, Kam Eshghi: Inside Solid State Drives (SSDs) . Springer, 2012, ISBN 978-94-007-5146-0 , pp. 60 ff . ( limited preview in Google Book search).