IP core

from Wikipedia, the free encyclopedia

In microelectronics, an IP core (from English intellectual property core ) is a prefabricated functional block of a chip design that can be used in many ways (in the sense of construction plans) in the semiconductor industry . This includes intellectual property (Engl. Intellectual property ) of the developer or manufacturer and is licensed as a rule or hinzugekauft to integrate it into its own style.

Companies such as ARM Limited and MIPS Technologies ( processors ), Imagination Technologies (graphics cores) or CEVA, Inc. ( digital signal processors ) have specialized in designing parts or entire integrated circuits and selling licenses for these designs. Chip manufacturers then expand the licensed cores with additional peripheral components such as graphics cores, analog-to-digital converters as well as standardized interfaces in order to develop a system-on-a-chip for a specific application. The licensee reduces his risk by purchasing standard designs that have been tested many times, accelerates development time and simplifies software development when licensing processors. Depending on the application, the IP cores can be manufactured as ASIC or, for smaller designs, loaded into an FPGA as a configuration . The so-called "verification IP" is related to this IP that can be implemented in hardware. These are reusable software components that are used to verify hardware and, in particular, hardware IP cores.

IP cores for ASICs

A distinction is made between soft IP and hard IP core:

  • A soft IP core exists in the form of source code in a special hardware description language such as Verilog or VHDL . It can also be available as a network list already synthesized by the manufacturer , as a textual description of a circuit diagram . In this case one speaks of Firm-IP-Cores. In the case of commercial IP cores or IP cores with procedural secrets, the network list can also be available in encrypted form.
  • A hard IP core is a block with an already completed layout. Thus, the user can hardly make any changes to the IP and is tied to a process. To protect procedural secrets, a user often only receives a black box representation of a purchased hard IP core. The content is then only known to the foundry or a service provider who completes the layout of the chip. Analog circuits are always implemented as hard IP.

IP cores for FPGAs

A distinction is also made between soft cores and hard cores for IP cores for FPGAs :

  • Soft cores are available as source code or in the form of a network list and are implemented in the freely programmable area of ​​an FPGA. Soft cores thus correspond to the soft IP in ASICs. An IP core that is available in the source code can be used for both FPGAs and ASICs. In contrast, soft cores in the form of a network list can only be used with a specific FPGA model. Therefore there are often IP core generators with which the user can generate net lists for the various FPGA models of a manufacturer. Typical examples of soft cores are processor cores optimized for the respective FPGA architecture, such as the Nios II from Altera or the MicroBlaze from Xilinx , which, together with their programs, can be integrated into the FPGA if required. Another class are interface controllers for buses such as SPI and I2C , but also controllers for controlling external DRAM memory modules.
  • Hard cores are unalterably integrated into the chip of the FPGA as a finished circuit by the manufacturer. The advantage here is that hard cores occupy less chip area and can usually work faster than soft cores implemented with freely programmed logic. The disadvantage is the impossibility of making your own adaptations or porting (migrating) to other logic families that do not have the mostly very specific hard cores. Most FPGAs contain dedicated memory blocks as well as ready-made multipliers, which are instantiated by the synthesis software if required. Larger FPGAs sometimes also offer complete processors such as the PowerPC cores in FPGAs of the Virtex series from Xilinx. In addition, interface controllers for more complex interfaces such as Ethernet as well as SerDes for the implementation of high-speed interfaces such as PCI-Express and S-ATA can be included.

Web links

Individual evidence

  1. Frank Kesel, Ruben Bartholomä: Design of digital circuits and systems with HDLs and FPGAs: Introduction with VHDL and SystemC . Oldenbourg Verlag, 2013, ISBN 978-3-486-73181-1 , p. 8 .