SerDes

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In digital technology, a serializer / deserializer ( SerDes for short ) is a pair consisting of a multiplexer and a demultiplexer that are used for serial data transmission between two parallel endpoints. The parallel data to be transmitted are converted in the serializer into a serial data stream with a high bit rate, transmitted serially, and output again in parallel in the deserializer for further processing. The serial interface, common transmission media are symmetrical signal transmissions using Low Voltage Differential Signaling (LVDS) or fiber optic cables (LWL), is transparent with regard to the parallel interface. The advantage of SerDes is the lower number of lines compared to parallel transmission and the avoidance of clock skew , which is particularly advantageous with backplanes .

construction

Principle of the serializer and deserializer with serial transmission in between

The serializer , in this context also called English Parallel In Serial Out (PISO) , typically and in the basic configuration consists of a parallel data input, word widths of 8 to 24 bits are common, the serial output and a clock line not shown in the figure , which indicates the arrival of a new data word. The deserializer , also called english Serial In Parallel Out (SIPO) referred to, is constructed almost a mirror image and consists of a serial input and parallel data output.

The primary basic function is implemented by shift registers , in addition SerDes modules have additional functional units for clock generation on the serializer side and functional units for clock recovery on the deserializer side. Various forms of phase locked loops (PLL) are used for this purpose.

There are four basic SerDes procedures which are shown in more detail below. The complexity of the individual procedures increases downwards.

Parallel clock SerDes

The serialized data stream is sent with a separate reference clock . The advantage is the somewhat lower circuit complexity. The disadvantage is that two lines are required for the transmission (serial data and clock line) and the problems of clock skew can only be reduced by additional measures. The first available SerDes procedures were based on this principle.

Embedded clock SerDes

In serial data transmission, the clock signal in the serializer additionally integrated ( English embedded ) and the deserializer wins from the receive clock. The advantage is that only one transmission line is required and problems due to clock signal deviations are reduced. The disadvantage is the significantly higher circuit complexity for synchronization and clock recovery.

8b / 10b SerDes

With this SerDes procedure, a line code based on the eponymous 8b10b code is also used. The advantage is that the resulting serial signal has no DC components and can therefore be transmitted via pulse transformers or fiber optic cables.

Bit-Interleaved SerDes

With the Bit-Interleaved SerDes, or “bit entanglement” in German, several serial data streams are interpreted as a parallel data signal by means of interleaving and combined with the appropriate line coding to form a higher-level, high-frequency data stream. This method is sometimes counted as part of the SerDes method, although it has functional overlaps with typical multiplex methods from the field of telecommunications networks for wide area data transmission such as the synchronous digital hierarchy (SDH) and SONET .

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  1. ^ A b Dave Lewis: SerDes Architectures and Applications. (No longer available online.) National Semiconductor, DesignCon, 2004, archived from the original on March 31, 2012 ; Retrieved March 8, 2013 . Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. @1@ 2Template: Webachiv / IABot / www.national.com