Phase locked loop

from Wikipedia, the free encyclopedia

A phase-locked loop , also called English phase-locked loop referred to (PLL) is an electronic circuit arrangement , the phase position and, related to the frequency of a variable oscillator via a closed control loop influenced so that the phase deviation between an external periodic reference signal and the oscillator, or a signal derived therefrom is as constant as possible. A special feature compared to other control loops is that the controlled variable - the phase - repeats itself after jumps of 2π; the regulation can therefore "lock" in at different relative phase positions.

The PLL is used in communications , control and measurement technology, such as for the implementation of filters , for modulation and demodulation, in digital communication systems for clock recovery and synchronization.


First mentions of analog phase locked loops can be found in British work from the early 1920s. The circuits were realized with electron tubes and served in the following years as a circuit part in the radio technology emerging at that time and were used in heterodyne receivers , among other things . The aim was to minimize the necessary coordination circles and to stabilize them during operation.

Important work on the fundamentals, based on the theory of feedback amplifiers , was provided in the 1930s by the work of Hendrik Wade Bode with the Bode diagram and Harry Nyquist with the Nyquist stability criterion . Based on this, phase locked loops were increasingly used in control technology to control actuators such as servomotors . As early as the 1950s, phase-locked loops were used for horizontal synchronization of televisions, and the first phase-locked loops were used to receive the emerging VHF radio programs as part of frequency demodulation . Applications in the field of television technology followed , in particular in the field of color television based on the NTSC television standard .

In the mid-1960s, PLL began to spread widely in consumer electronics such as radio and television sets. The analog control loops, which were discreetly implemented in the early days, were increasingly combined in integrated circuits (IC) and offered as finished components by companies such as Signetics . From this, popular phase locked loops developed in the electronics sector, such as the 74 4046 PLL circuit developed by RCA . This TTL circuit is now implemented using CMOS technology (the fast, TTL-compatible version is the 74HCT4046 and the slower, more energy-saving version is the CD4046). The IC found widespread use and will also be offered by various manufacturers in 2020.

At the beginning of the 1980s, the first digital phase-locked loops were developed, which are essential for the field of digital signal processing and the associated synchronization of transmitter and receiver devices. Phase-locked loops have also been modified in various ways, such as the Costas Loop for demodulating digital transmissions.


Structure of a phase locked loop

The simplest form of a PLL consists of four components in a control loop :

  1. A phase comparator, which is also called a phase comparator or phase detector , (here provided with a link to the circuit of a phase frequency detector, which is explained below). This compares to its two inputs the phase of the input signal Y (s) (optionally divided by n) with the phase position of the controlled oscillator and supplies an output signal e (s) the in the control art as the error signal ( Error signal hereinafter) . After filtering, E (s) becomes an analog signal which should correspond to the phase error.
  2. A loop filter with the transfer function F (s), to which the error signal E (s) is fed and which supplies the control signal or control signal C (s) at its output . The loop filter, together with a factor k, is the controller.
  3. A controllable oscillator. In analog circuits, usually in the form of a voltage controlled oscillator (Engl. Voltage controlled oscillator implemented, VCO), for example, by a capacitance diode can be changed in its frequency. With regard to the phase to be regulated, a VCO is an integral term K o / s, because a phase is the integral of a frequency. The factor K o = 2π * Δf o / ΔU C is called the VCO slope. For complete modeling, this integral term is preceded by an adder from which the expected control voltage of the VCO is to be subtracted. The loop filter then supplies the VCO control voltage, while the voltage zero is set at the integral element for the steady static case. That has to be the case, because an integral term only comes to rest when its input variable is zero. - For digital PLLs are numerically controlled oscillators (Engl. Numerically controlled oscillator NCO) common. The frequency of this oscillator can be influenced within certain limits via the control signal C (s), which is fed to the phase detector either directly or via an additional frequency divider.
  4. A frequency divider with the division factor n, which divides the output phase O (s) of the oscillator by n and thus leads the fed back phase Z (s) to the phase comparator. The transfer function of the frequency divider is called Z (s) / O (s) = 1 / n. For mathematical reasons, all phases are given in radians.

In the steady state, this arrangement results in tracking of the oscillator frequency, so that the phase Z (s) follows the reference phase Y (s). Depending on the application, either the error signal E (s), the control signal C (s) or directly the oscillation generated by the controlled oscillator with its phase O (s) is considered as the output of the PLL . The three basic components are selected differently depending on the application and determine the dynamic operating behavior of the control loop. Analog multipliers are used as phase detectors in analog PLLs, for example a Gilbert cell , which has an approximately linear transmission behavior in the range of small error values, at E (s) close to the value 0. The Gilbert cell is also functional in the event of digital override, although this turns it into an XOR element. Exclusive-OR gates or sequential logic circuits in the form of flip-flops are used in digital PLLs . Up / down counters with 1 bit memory depth are very common, especially in analog PLLs, which not only compare the phase in a highly linear manner, but also indicate the slip direction in the event that the PLL is not yet engaged. With the information about the slip direction, the controller pulls the VCO frequency so far that the phase-locked loop can lock into place. Without such a phase frequency detector (PFD), capture can be achieved by slowly sweeping the VCO. The type of phase detector thus determines the so-called locking behavior of the PLL. If, in an undesired case, the input frequency remains next to the frequency of the oscillator divided by n, there will be permanent phase slip with unsteady behavior. The PLL system is then not engaged.

Order of a PLL

Some traditional PLL books deal with the question of the appropriate controller under the term “organization of a PLL”. An ordinal number is defined differently here than with the filter . The linear loop filter , including the ripple filter, also has a low-pass behavior, but the corner frequency is relatively high. For a better overview, the capacitor of the ripple filter is missing in simplified circuits, and the associated pole is initially irrelevant. A dead time element , as it arises in the PFD, is not taken into account for the time being.

The transfer function of the open loop G (s) ( open-loop transfer function ) consists of the product of the transfer functions that lie in the loop:

Specifically for F (s) = 1, it follows that G (s) = ω As / s, where the counter ω As = k · K o / n now corresponds to a primary target for the 0 dB bandwidth, according to which k is has to judge. k is defined here in volts / rad. ω As / s now determines the main asymptote in the Bode diagram , which falls at −20 dB / decade.

For one of the possible transfer functions of the closed control loop H (s) = O (s) / Y (s) ( closed-loop transfer function ) follows:

A bit above ω As , H (s) always retains the amplitude response −20 dB / decade, regardless of the choice of the following controls.

First order

In a first-order PLL, the error signal E (s) is fed directly to the controlled oscillator as a special feature , so E (s) · k · F (s) = C (s) with F (s) = 1 and with a constant one applies Factor k which only expresses a gain or attenuation. Such a proportional controller with the factor k , which can only be freely selected within narrow limits, must be able to generate the VCO control voltage. It only achieves this for the desired steady-state case if the phase comparator delivers a value that still fits its limited characteristic. Otherwise the PLL can never lock. A first-order PLL is therefore only of practical importance in the event that an adder that is present in hardware adds a suitable, previously known value to E (s) · k .

Second order

If such values ​​are not available, an integral controller is required, more precisely a proportional-integral controller, which ensures that the error E (s) at the phase comparator can become zero. This advantage is offset by the disadvantage that the first settling is slower and that more chip area is required for integration because of a capacitor. To stabilize the control loop, the proportional-integral controller changes to the behavior of a proportional controller from a certain frequency. This is the PI controller F (s) = 1 + ω PI / s, as it is used in a so-called second-order PLL. ω PI must be less than ω As . Since F (s) now assumes the gain 1 again for frequencies greater than ω PI , G (s) retains its 0 dB passage close to the desired bandwidth ω As , with the 0 dB intersection of the main asymptote in the Bode diagram being the scale again. The PI element adds an asymptote that is now twice as steep, which intersects the main asymptote at ω PI and the 0 dB axis at ω n = ω As / (2 * ζ). Here, the damping factor Eigen and natural frequency ω n are elements of a second order polynomial, which results in the denominator of H (s).

In order to retain the primary design parameter ω As in all further considerations and not to lose sight of a target, it is advantageous to eliminate ω n in further equations with ω n = ω As / (2 * ζ).

Third order

If you want to keep the definition of the atomic number simple, you can limit yourself to the number of integral terms that are in the loop. For example, if there is a PI controller in front of the PI controller, the result is a third-order PLL with the following open loop transfer function:

According to the general Nyquist criterion , the system is stable. The first PI controller assumes the value zero at the input and output in the steady, static case. Third order PLLs make it possible to reduce phase errors while maintaining a constant chirp rate .

In the literature sources given below, the different types of PLLs are classified and tabulated in different types depending on the order and within an order.

Operating areas

Operating ranges of a PLL

The deviation of the input frequency from the frequency f c generated by the controllable oscillator describes different operating ranges of a PLL which are essential for the behavior of the control loop. A distinction is made between the locked operating range ( lock ) of the PLL, in which there is stable control behavior, the locking behavior, where the control loop possibly changes into the locked stable operating state, and the unlocked, free-running operating state.

The graphic on the right shows the four main operating ranges, the deviation of the input frequency being symbolized by a horizontal, symmetrical deviation from the central local frequency f c . The exact limit values ​​depend on the type of phase detector and the loop filter. The areas mean:

  1. Holding area (. English hold-in range ): Is the highest range, the phase locked loop can be followed in this area at a slow and not abrupt change of the input frequency. In this case there is control behavior.
  2. Pull -in range : In this area, the PLL can only change from the unlocked state to the locked state by skipping one or more periods.
  3. Pull -out range : When a frequency jump is applied to the input of the locked PLL, it can follow a period in this area without skipping. In this case, too, there is control behavior.
  4. Lock -in range : In this area, the PLL can change from the unlocked state directly to the locked state without skipping a period. This range is the narrowest range around the oscillator frequency.

Outside the holding area, there is the unstable free-running operation, in which it is not possible to lock into place or to hold a previously engaged operation.

Digital PLL

Phase locked loops can also be implemented as so-called digital PLL , or DPLL for short , in the context of digital signal processing . The transition from a time-continuous system to a time-discrete system is essential, and the discrete Z-transformation takes the place of the continuous Laplace transformation for analysis . One advantage of DPLLs is that they are easier to reproduce.

The classification of the extent from which a PLL is to be classified as a DPLL is not uniform in the literature. So only part of the PLL, for example only the loop filter, can be implemented as a digital filter . Typically, the design methods of an analog PLL are used as the basis for the DPLL. With All-DPLLs , the complete control loop including NCO is built up in digital circuits.

So-called software PLLs , which implement the control loop as a sequential program in a digital signal processor and are mostly used at low frequencies, also belong to the area of DPLLs . In software PLLs, complex phase detectors based on the Hilbert transformation are also used.

Differences to other oscillator designs


  • Although the generated frequency can be varied (in steps), it has the same relative (long-term) stability as the reference oscillator, which works at a fixed frequency and can therefore be very frequency-stable.



PLLs cover a wide range of applications and some application areas are described in the following section as examples.

PLL as a follow-up filter

If the frequency and phase of the reference signal are considered as the input variable and the oscillator signal as the output variable, the arrangement described behaves similarly to an electrical bandpass , the transmission properties being essentially determined by the dimensioning of the loop filter . Of particular importance when using the PLL as a bandpass filter is the fact that it is automatically tracked to the frequency of the input signal. At the same time, this arrangement offers the possibility of realizing very small tracking bandwidths. It is therefore particularly suitable for the regeneration of noisy signals of variable frequency.

PLL as a demodulator and modulator

With the reference signal as the input variable and the oscillator control voltage as the output variable, the PLL is suitable for use as an FM demodulator as long as the modulation frequency remains smaller than the tracking bandwidth. The above-described filter effect of the PLL is retained so that extremely disturbed signals can also be demodulated.

If the output voltage of the phase detector is used as the output signal, the PLL can be used as a demodulator for phase-modulated signals. In this case, the tracking bandwidth must be selected to be smaller than the lowest modulation frequency. In the era of analog signal processing, PLL-based phase demodulators had temporarily gained importance in satellite communications.

Analogous to the functions as a demodulator, the PLL can be used as a PM and FM modulator. A PLL system can be operated frequency-modulated with a selectable stroke . But without compensatory measures, the modulation is filtered by the system.

Frequency synthesis

Basic circuit of a PLL control loop
Phase noise of a PLL oscillator in the SW range. In the case of a quartz oscillator, the corresponding characteristic would be an almost vertical line on the left edge of the picture.

One area of ​​application of the PLL is frequency synthesis. The picture opposite shows a block diagram of a PLL-based frequency synthesizer. A VCO (voltage controlled oscillator) generates the output signal. A frequency divider is provided in the feedback branch of the PLL , which divides the VCO frequency down by an adjustable factor before the phase detector . The reference signal of the PLL is typically provided by an accurate and stable crystal oscillator .

In the locked state, the VCO is regulated to a frequency that is greater than the frequency of the reference signal by the division factor. By changing the division factor, the frequency of the VCO can thus be set to precisely integer multiples of the reference frequency. An essential aspect is that the accuracy and stability of the fixed reference frequency also apply to the adjustable output frequency.

The arrangement described can be built with the components available today at low cost in a very small space and is used on a large scale, for example, in mobile telephones, radios, television tuners and radios. Typical output frequencies are a few hundred MHz, typical reference frequencies are a few 100 kHz. The frequency divider and phase detector are mostly implemented in an integrated circuit, while the VCO and the loop filter are often built discretely.

Important considerations when designing a PLL frequency synthesizer are the spectral purity of the output signal, the frequency resolution, and the lock-in time required for a frequency change. The spectral purity is essentially determined by the properties of the VCO, but also by the noise properties of the other components as well as by an appropriate structure (shielding, filtering).

In the system described above, the frequency resolution is the same as the reference frequency. The locking time depends essentially on the control bandwidth, which cannot be freely selected, but has to be optimized with regard to the reference frequency used and the spectral purity of the output signal. The dimensioning of practical systems shows that a high frequency resolution contradicts the requirements for spectral purity and short locking times.

This contradiction can be resolved by using a frequency divider that divides the VCO frequency by fractional factors. For this purpose, the partial factor must be varied over time so that the desired fractional setting value results on average. At the output of the phase detector, however, a disturbance variable arises which must be compensated or filtered with suitable countermeasures (e.g. delta-sigma method). With PLL synthesizers constructed in this way, arbitrarily fine frequency resolutions can be achieved with the shortest locking times and very high spectral purity.

Communication technology, measurement technology

PLLs are suitable for generating stable frequencies up to the GHz range (radio technology), generating programmable frequencies, generating high-frequency clocks for computers and synthesizer tuners, as this circuit technology enables very precise selection and control of frequencies . On the one hand, it is possible to generate a precise output frequency with a fixed reference frequency (quartz oscillator) and a variable feedback frequency divider, which corresponds to the synthesizer principle mentioned. On the other hand, a variable frequency can be multiplied by a fixed factor using a fixed feedback frequency divider.

In addition to being used as frequency generators, PLL circuits are mainly used for demodulating frequency or phase modulated signals, for clock synchronization and clock recovery.

Depending on the application for which the PLL is used, there also differs where the output signal is tapped. The frequency of the oscillator is z. B. used in frequency modulators, when used as a demodulator of an FM signal, the tuning voltage of the VCO.

Clock recovery

Some data streams, especially serial, synchronous data streams (such as the data stream from the magnetic read head of a hard disk ), are sent or read from the storage medium without a separate clock signal. For clock recovery from the received signal, a special line coding of the useful data to be transmitted is necessary, as represented by the Manchester code , for example .

Clock synchronization

If a pulse was sent in parallel with the data stream, it must be reprocessed before it can be used to process the data. However, this takes some time, so that the clock and data are initially no longer synchronous with one another. The PLL ensures that the regenerated clock and the original clock (and thus the data) are synchronized again.

Energy Technology

A PLL is also used in active systems for power factor correction to obtain the phase position from the external conductor voltages . With the help of the phase angle, a regulation can be carried out which ensures that the external conductor currents have the same phase position as the phase voltages. This means that the fundamental power factor can be brought to values ​​just below 1 and the line network is not loaded with reactive power .


A delay-locked loop (DLL) has a similar structure to a PLL, but does not have its own oscillator and instead works with an adjustable delay element . In the field of digital frequency synthesis , the element of direct digital synthesis (DDS) plays a role, which is used as an NCO in the context of a digital PLL . The Frequency Locked Loop (FLL) has a modified discriminator and belongs to the group of PLLs in the literature.


  • Donald R. Stephens: Phase-Locked Loops For Wireless Communications. Digital, analog and optical implementations. 2nd Edition. Kluwer Academic Publishers, 2002, ISBN 0-7923-7602-1 .
  • Dieter Scherer, Bill Chan, Fred Ives, William Crilly, Donald Mathiesen: Low-Noise RF Signal Generator Design . Hewlett-Packard Journal, February 1981.
  • Bar-Giora Goldberg: Digital Frequency Synthesis Demystified - DDS and Fractional-N PLLs . LLH Technology Publishing., Eagle Rock 1999, ISBN 1-878707-47-7 .

Web links

Commons : Phase-locked loops  - collection of images, videos and audio files

Individual evidence

  1. ^ JH Vincent: On Some Experiments in Which Two Neigboring Maintained Oscillatory Circuits Affect a Resonanting Circuit . Proceedings Royal Society, Vol. 32, Part 2, 1920, pp. 84 to 91 .
  2. H. de Bellescise: La réception Synchronous . Onde Electrique, 11th edition, 1932.
  3. Hendrik Wade Bode: Relations Between Attenuation and Phase in Feedback Amplifier Design . Bell System Technical Journal, 19th Edition, 1940, pp. 421 .
  4. Harry Nyquist: Regeneration Theory . Bell System Technical Journal, 11th Edition, 1932, pp. 126 .
  5. ^ J. Ruston: A Simple Crystal Discriminator for FM Oscillator Stabilization . Proceedings of the IRE, 39th Edition, No. 7, 1951, pp. 783 to 788 .
  6. ^ AB Grebene, HR Camenzind: Phase Locking As A New Approach For Tuned Integrated Circuits . ISSCC Digest of Technical Papers, 1969, p. 100 to 101 .
  7. Data sheet of PLL 4046 (PDF; 442 kB) from NXP (Philips) ( Memento from February 6, 2009 in the Internet Archive )
  8. ^ WC Lindsey, CM Chie: A Survey of Digital Phase-Locked Loops . Proceedings of the IEEE, 69th Edition, No. 4, 1981, pp. 410 to 430 .
  9. ^ J. Tierney, CM Rader: A Digital Frequency Synthesizer . IEEE Transaction on Audio and Electromagnetics, Vol.AU-19, 1971, p. 48 to 57 .
  10. Technical Brief SWRA029 - Fractional / Integer-N PLL Basics (PDF; 6.9 MB) from Texas Instruments.