Delay-locked loop

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A delay-locked loop (DLL) is an electronic circuit that has a structure similar to a phase-locked loop (PLL). The main difference to the PLL is the lack of a voltage-controlled oscillator , only the clock signal present at the input is used as the output signal with a time delay. For this purpose, an adjustable delay chain is provided, from which the name of this circuit is derived. The advantage of this loop compared to a phase-locked loop is the lower circuit complexity.


Simplified block diagram of a DLL

Viewed from the outside, the DLL can be viewed as a negative time delay due to its loop (feedback). An essential component of a DLL is a variable delay chain, which is formed by a chain of individual elementary delay elements with a fixed delay time. The instantaneous delay of the entire chain depends on the phase position between the input and output signal and is set dynamically during operation via a control signal. Depending on the type and application, the phase discriminator used for this can compare for minimal errors or for a configurable phase angle other than zero.

Analog DLLs work with the following two types as a delay chain:

  • Current-Starved Inverter
  • Shunt-Capacitor Delay Stage (also Capacitor-Loaded Inverter Delay Line)

In digital DLLs, the control signal generated by the phase discriminator acts on a multiplexer , which minimizes the phase error in discrete steps. The output signal of the DLL is then present at the output of this multiplexer. In DLLs implemented in practice, additional loop filters are used between the phase discriminator and the delay chain , which influence the dynamic behavior of the control loop.

Areas of application

A DLL is primarily used to adjust the phase position of a freely running clock signal in the area of synchronous, digital circuits in order to achieve frequency-independent phase shifts. DLLs are used, for example, in FPGAs from the manufacturer Xilinx to process external clock signals and to compensate for gate delay times . DLLs are also used in most DDR SDRAMs to control the timing of the outputs in relation to the clock signal (exception: a PLL is used in GDDR5 modules).

These circuits are also used in GPS receivers to follow a satellite signal. An extension to the DLL is the VDLL Vector-Delay-Lock-Loop , which promises tracking under even more adverse circumstances, but is currently still the subject of research.


  • Donald R. Stephens: Phase-Locked Loops for Wireless Communications - Digital, Analog and Optical Implementations . 2nd Edition. Kluwer Academic Publishers, 2002, ISBN 0-7923-7602-1 , p. 186-194 .

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