Synchronous circuit

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A synchronous circuit is a digital circuit consisting of edge - controlled flip-flops which are all clocked from a central clock signal . Usually all complex integrated digital circuits such as microprocessors or various types of digital peripheral components are constructed as synchronous digital circuits, since this allows controllable time relationships between the individual circuit parts. Synchronous circuits are the preferred design method for digital circuits in Field Programmable Gate Arrays (FPGAs).

Synchronous circuits with feedback can be described as a synchronous switching mechanism or synchronous state machine. Transitions from one state to the next take place in the fixed time pattern of the clock signal. Typical synchronous switching mechanisms are microprocessors which are operated with a central clock as a so-called single-ended system. There are also multiple clock systems in which all clock signals have a defined phase and frequency relationship to one another and are referred to in the broader sense as synchronous.

The contrast is represented by asynchronous circuits which do not have a central clock signal and, apart from a few exceptional cases, have little practical relevance due to the more difficult handling in more complex circuits.


The essential feature of digital synchronous circuits is the clock frequency . In the case of edge-controlled flip-flops, which serve as elementary storage elements, the state at the input is recorded in the memory with the clock edge and held until the next clock edge. The period, that is the time between two adjacent clock edges, indicates the maximum "processing speed" of a synchronous circuit. The clock frequency upwards and the period duration downwards are limited, among other things, by the signal propagation times of the data signal paths between the individual stages and the times that are required for logical links between the memory elements. It should be noted that not only the data signals have a certain maturity, but also the clock signal, resulting in unwanted race conditions and clock skew ( English clock skew may result).


  • Jürgen Reichardt, Bernd Schwarz: VHDL synthesis: design of digital circuits and systems . 5th edition. Oldenbourg Wissenschaftsverlag, 2009, ISBN 978-3-486-58987-0 .

Individual evidence

  1. Clock Skew and Short Paths Timing (PDF; 884 kB), Application Note AC198, 2011, engl.