Clock offset

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The clock skew (engl. Clock skew ) is a phenomenon of synchronous circuits and synchronous data transmission method . It describes the time difference between the arrival of a clock edge at the first element to be considered (e.g. a flip-flop ) and the time of arrival at a second element.

Depending on the selection, the clock offset can assume positive or negative values; the largest difference in terms of amount describes a limit for the upper clock frequency. Ideally, the clock skew is zero, which is not physically feasible. In real synchronous circuits, the amount of the clock offset is in the range of a few 10 ns, depending on the technology,  and can be reduced to a few picoseconds through special measures. To minimize this, the clock signal is distributed in synchronous digital circuits in separate clock distribution networks , which can be structured like an H-tree . Further possibilities are delay-locked loops , which allow a targeted phase shift in the clock signal for certain circuit areas.

Occurrence in real circuits

Synchronous digital circuit with two D flip-flops to illustrate the clock offset t dc

The simplest synchronous circuit shown here, which consists of two D-flip-flops connected in series as storage elements, serves for the description . Each D flip-flop takes the state with a rising edge at its input D and outputs this value to its output Q from. In an ideal circuit without delay times, the first flip-flop takes over the state of the input line D , with the second clock edge the second flip-flop takes over.

In a real circuit, additional transit times occur, both through the flip-flops and along the different lengths of the supply lines: The clock signal at point CLKB for the second flip-flop is shifted in time compared to the clock signal at point CLKA due to the spatial expansion - this time difference is called the clock offset t dc designated. Together with the transit times through the flip-flops, shown as an arrow in the timing diagram, and the transit time along the data path , which represents a switching network, this can lead to the data signal Q at the output only changing one clock period later than when the transit time would be correspondingly shorter on the data path. This results in the following timing problems of synchronous circuits that must be observed, which must be avoided when designing the circuit by choosing the topology or clock frequency:

  1. The change in the data signal at input D2 can fall within the range of the rising clock edge through appropriate times. In this case, the so-called setup and hold times of the second flip-flop are violated. The setup and hold time describes a blocking range shortly before or after a clock edge in which the value of the input must not change. If this happens anyway, metastable states in the flip-flop can result.
  2. As shown in the figure, the runtimes can lead to an additional time shift by one clock period, which can lead to subsequent problems in switching mechanisms, i.e. circuits with feedback, since invalid states occur in the state machine for one clock period, for example.

To avoid these timing errors, special timing analysis tools are used in the development of synchronous circuits , which determine the runtimes using the known technology parameters of the semiconductor chip and can identify possible dynamic status errors in the specific circuit design in the network list .

Individual evidence

  1. ^ EG Friedman: Clock Distribution Networks in Synchronous Digital Integrated Circuits . tape 89 , no. 5 . Proceedings of the IEEE, 2001, pp. 665-692 , doi : 10.1109 / 5.929649 .
  2. ↑ S. Tam, DL Limaye and UN Desai: Clock Generation and Distribution for the 130-nm Itanium 2 Processor with 6-MB On-Die L3 Cache . In: IEEE Journal of Solid-State Circuits . tape 39 , no. 4 , 2004, p. 636-642 , doi : 10.1109 / JSSC.2004.825121 .