Metastability (digital circuit)
Metastability is a mostly undesirable property in digital technology , and when it occurs in digital circuit parts such as flip-flops, these remain in undefined intermediate states between the stable states for a certain time. In the usual binary digital technology, metastable states are characterized by voltage states between the two stable voltage levels for logic 0 and logic 1 . These intermediate states can lead to unforeseen errors and failures if the metastability is not observed.
description
The simplest form of digital circuit is the RS flip-flop . This feedback circuit has two stable states, logical 0 (reset state) and logical 1 (set state). These two stable states are expressed by two voltages near the lower and near the upper operating voltage. In the event of a small disturbance in these stable voltage levels, the circuit returns to the respective stable state - this is what constitutes the storing effect of the circuit. In addition, there is a metastable operating range. This is roughly in the middle of the operating voltage, where the operating behavior is not determined.
Ideally, the RS flip-flop could remain indefinitely in this metastable area. As a result of small physical interference effects such as noise , this metastable state will in practice, in the vast majority of cases, usually tip over into one of the two stable states within very short times in the range of a few nanoseconds. However, it can only be statistically predicted after which time this transition will happen by chance into one of the two stable states.
Metastability upon scanning
Typical problem cases are the sampling of an arbitrarily changing, i.e. not time-synchronized, signal with a clock edge-controlled D flip-flop . D flip-flops represent the elementary storage elements in many digital circuits such as FPGAs and ASICs : With the active edge of the clock signal , the D flip-flop scans the state at its input D , saves this state and sends it to its output Q until the next active clock edge out. In order to function correctly and to avoid metastability, certain times must be observed: The input signal D must not change for a certain short period of time before and after the active clock edge, i.e. H. the input signal must be constant at logical 0 or logical 1 in this time interval of the sampling . In the English-language specialist literature, these blocking times are referred to as setup and hold time .
In the case of external signals that are not synchronized with the clock and that are fed to the D flip-flop at its input D , this condition cannot always be met: The blocking time (setup and hold time) can be violated, which means that the voltage level is not allowed Sampling time at which the D flip-flop can fall into a metastable state. This problem also occurs when a digital signal is to be transmitted between two clock domains that are not synchronous with one another, as shown in the figure on the right with the associated time curves: The left D flip-flop is controlled with the clock A (CLK-A), the other two flip-flops by an asynchronous clock signal B (CLK-B).
In the first D flip-flop in the clock domain B there may be certain times when the signal change D in just happened at a sampling with clock signal B coincides to a metastable state at the signal D s view, shown in the timing diagram as uneven course. In many cases, this metastable state ends after a short time, and the input flip-flop then accidentally flips into one of the two stable states. If the input signal does not change, the metastable state is ended by a renewed and in this case stable sampling at the latest after one clock period. So that subsequent digital circuit parts are not impaired in their function by the undefined voltage curve, another D flip-flop is connected downstream, which is controlled by the same clock B and results in a stable transition at the final output D out . This results in an additional latency of one clock period due to the successive double sampling.
It is essential that the metastable situation cannot be completely avoided by any measure whatsoever. Every "suggested solution" for absolute avoidance is always based on a mistake in thinking that ignores the occurrence of metastability at any point. By connecting several scanning stages such as flip-flops in series, only the probability of the metastable state occurring can be reduced as much as required. In the example given above with the second D flip-flop, adherence to the setup and hold times of the second flip-flop cannot be guaranteed if the first flip-flop is in the metastable state. In the case of logic circuits common in the market around 2010, such as in FPGAs, the dwell time in the metastable state is less than 1 ns with a probability of 99.9% of the switching processes. This makes it possible to determine the overall probability of a malfunction by scanning e.g. B. 10 ns to lower irrelevant values.
literature
- Steve Kilts: Advanced FPGA Design - Architecture, Implementation, and Optimization . Wiley-Interscience, 2007, ISBN 978-0-470-05437-6 , Chapter 6: Clock Domains.
- Randy H. Katz: Contemporary Logic Design . The Benjamin / Cummings Publishing Company, 1994, ISBN 0-8053-2703-7 , 6.4: Metastability and Asynchronous Inputs.