Signal edge
With digital signals, signal edges are the transitions between the signal states high ( H ) and low ( L ), referred to as rising and falling edges.
A distinction is made between rising edges (L / H transition [t2] and [t6] ) and falling edges (H / L transition [t4] and [t8] ). H stands for high , live and logic 1 , L for low , logic 0 . Numerous digital switching elements use the edges as triggers , for example in counters and JK flip-flops . These are referred to as positive or negative edge-triggered inputs of the blocks with the same meaning .
Ideally - as shown in the lower part of the drawing - edges are direct jumps without a time delay. These are a theoretical ideal state. With increasing ohmic load on the outputs ( fan-out ), higher capacities or inductances in the signal-carrying line, the edge steepness deteriorates and the rise and fall times increase. With inductive properties of the signal line or the load, overshoot can occur.
The edge steepness, i.e. ultimately the time of the transition, is important for the switching speed and signal quality. With long switching times that cause a low edge steepness or noisy signals, it may be necessary to use a Schmitt trigger instead of a normal input . The noise is filtered with the hysteresis of the input of the Schmitt trigger.
A monostable toggle stage is the principle of stairwell lighting and is installed between the switch and the lamps. This circuit reacts to the switch-on edge and generates the switch-off edge after the set time has elapsed. In the case of retriggerable monostable multivibrators, the switch-off edge is delayed by the set time. In the application, this differs whether the time for the light to go out can be extended by pressing the light switch a second time.
The phase detector as the core of the phase locked loop detects edges in order to synchronously control frequencies and speeds on the edges. " Edge demodulation " is another name for frequency modulation and is demodulated with a feedback phase-locked loop , whereby the time differences are fed to the control of the AFC and processed as a demodulated signal.
Targeted signal delays are built into clock signals , with negative effects on the edge steepness, in order to prevent the clock from possibly leading the data signals. This concerns synchronous data transmission , in which the data signals are taken over on the clock signal with edge control.
See also
- Duty cycle (= Duty cycle)