Yield (semiconductor technology)

The yield ( English yield ) in the manufacture of integrated circuits (ICs) is used as a measure for evaluation of the production process or the chip designs. As part of the trade secret, it is usually not published by the manufacturers or is even kept secret.

general definition

In general, the yield can be defined as the proportion of usable or deliverable parts of the total number of parts . ${\displaystyle Y}$ ${\displaystyle N_{\text{lieferbar}}}$ ${\displaystyle N_{\text{gesamt}}}$

${\displaystyle Y={\frac {N_{\text{lieferbar}}}{N_{\text{gesamt}}}}}$

Typical types of yield are

• the line yield ( English line yield also wafer fabrication yield ; proportion of the wafers processed up to the final electrical test of the total number of wafers started) and
• the chip yield ( English chip yield and the yield or total yield wafer ; proportion of chips from the total number of chips on a wafer supplied to the final assembly or the customer)

In addition, there are numerous other categories, the names of which are derived from the evaluation test used:

• Wafer sort yield : The chip yield after the electrical test of the integrated circuits (chips) usually before the wafer is separated,
• wafer package yield : The yield of deliverable products after separation and introduction into a housing,
• final test yield : The yield after the electrical test of the integrated circuit in a housing (except for bare chips ) and
• burn-in yield : The yield of deliverable products after the burn-in test.

If the yield factors are specified with respect to their number of inputs instead of the original number of chips on the wafer, then the total yield is calculated from the product of the individual elements mentioned above, including the line yield. It must be noted that with products that consist of several individual chips, such as multi-chip modules or system-in-package , more complicated models must be used to calculate the total yield.

Another possibility to categorize the yield is to classify it according to the type of failure; a distinction is made between functional and parametric yield . The functional yield is understood to mean the proportion of fully functional products. In other words, products that are not affected by "hard failures" such as short circuits or open conductor paths. However, there are also cases in which functional products do not meet the specifications for one or more electrical parameters, such as switching frequency, power consumption, noise level or the number of functioning redundant sub-units. These are then also not considered to be functional and recorded as parametric yield.

Chip yield

The chip yield describes the ratio of functionally manufactured chips from the production process to the maximum number of chips on the wafer.

For the manufacturer, the chip yield is a decision point in production, as it is an essential point for the economic evaluation of production. As a rule, depending on the level of development in production, the yield is also used as an assessment for the further procedure. Therefore, a chip yield in the range of the desired or even maximum yield expected due to a typical defect density can signal the start of mass production. On the other hand, the chip yield can also be an indication of major problems in production. For example, a yield of less than 50% in a manufacturing process that has been in use for a year is considered catastrophic if the target value is actually over 90% at this point in time.

The sweet spot is the best possible practical yield towards the end of the life span of a semiconductor component - after the production processes have been further optimized, the sweet spot should be as close as possible to the theoretically achievable yield based on yield models.

Maximum number of chips on a wafer

The maximum number of (whole) chips on a wafer is required to calculate the chip yield. Simplistic can be assumed to be the upper limit of usable chips that results from the wafer surface (based on the wafer diameter ) divided by the area of an individual The ( ): ${\displaystyle d}$ ${\displaystyle A_{\text{Die}}}$

${\displaystyle {\text{DPW }}={\frac {\frac {\pi \,d^{2}}{4}}{A_{\text{Die}}}}}$

For any wafer diameter and the desired IC size, the number of complete "dice per wafer" (DPW) can be approximately calculated as follows:

${\displaystyle {\text{DPW}}=d\pi \left({\frac {d}{4A_{\text{Die}}}}-{\frac {1}{\sqrt {2A_{\text{Die}}}}}\right)}$

The error in these estimates can no longer be neglected even with medium chip sizes, since the area at the edge of the round wafer is increasingly occupied by incomplete areas and this area increases with the chip size or the longest chip side. In addition, there are other restrictions in production, such as

• Non-uniformities at the wafer edge and the thus introduced wafer edge exclusion ( English wafer edge exclusion ) for the evaluation of a chip over the entire area located on the wafer as the "usable" chip,
• the width of the test and saw trenches between the individual chips
• the size of blocked areas (where the wafer is "touched" by a machine, for example).

By optimizing the positioning of the dies (the wafer layout), the number of usable chips can possibly be increased compared to a symmetrical layout with the chip center or corner in the wafer center.

From a mathematical point of view, a wafer with a square dice leads in many cases to a better yield than with rectangular or even differently shaped chips.

Models for yield estimation

Three examples of the change in the yield on a 300 mm wafer depending on the die size (left: 40 mm × 40 mm; middle: 20 mm × 20 mm; right: 10 mm × 10 mm). With the same number of defects (red dot), the number of defective chips (yellow) is reduced and the yields are 35.7%, 75.7% and 94.2%, respectively.

The following important information is missing from this article or section:

Mathematical basics are missing - e.g. B. different calculation models such as "Murphy's yield integral" or the "negative binomial yield model" from Strapper

Help Wikipedia by researching and pasting it .

Physical defects that occur during the manufacture of an integrated circuit are a major factor influencing the chip yield (more precisely, the functional chip yield). In addition to particles, scratches and dislocations, this also includes incorrectly reproduced structures or problematic (local) fluctuations in layer thicknesses, structure sizes, misalignments and much more. In addition, the size of each chip is crucial because the larger a chip, the higher the proportion of a failed chips at the loss of yield ( yield loss ). In the extreme case of only one chip per wafer, a defect could make the difference between 100% and 0% yield.

Since the yield is an important parameter for the economic consideration of the production, models were developed at an early stage that allow an estimate of the expected yield based on a partly measurable or easily assessable defect density as well as other product and manufacturing properties. These models are usually a function of the defect density (defects per area) and the critical area ${\displaystyle D_{0}}$ ${\displaystyle A_{c}}$

${\displaystyle Y=f(D_{0},A_{c})}$

The evaluation of the defect density depends on the technology used, i.e. the minimum structure size . For example, a 40 nm larger particle is probably not important for a product in 180 nm technology, as it e.g. B. can not short-circuit two interconnects with a distance of about 180 nm. For a product in 28 nm technology with approx. 30 nm track spacing, however, the probability of a failure is quite high.

The most important models are briefly mentioned below. For additional information and derivations of the functions, please refer to the literature.

Poisson model

The Poisson model is based on the assumption of an even distribution of the defects over the wafer surface (and also from wafer-to-wafer). The form of the model function corresponds mathematically to the Poisson distribution :

${\displaystyle Y=e^{-A\cdot D}}$

Murphy integral model

The Murphy integral model (according to BT Murphy) does not assume the defect density to be constant, but must be added up over all chips using a standardized probability density function . The result is the general integral function: ${\displaystyle f(D)}$

${\displaystyle Y=\int _{0}^{\inf }e^{-A\cdot D}f(D)\,\mathrm {d} D.}$

Depending on the density function used - uniform, triangular, Gaussian distribution, exponential (according to Seeds) or according to the gamma function (according to Okabe, Nagata and Shimada or according to C. Stapper, also negative binominal model) - there are in part significantly different models that have proven to be more or less effective in the industry.

Increase in yield

To increase the yield, in addition to improving the production process, there is also the option of being able to switch off defective assemblies through appropriate product design and to continue using the remaining IC that is still (limited) functional. For example, a part of the cache of a processor can be deactivated (for example often with the Intel Celeron ) or with a multi-core processor one of the processor cores can be deactivated, as with the AMD Phenom and AMD Phenom II.

Performance classification

Usable ICs are often examined and classified according to various criteria, for example according to their performance characteristics with regard to power consumption or the maximum clock frequency achieved. They can be sold in different price segments or used for different purposes (e.g. for medical devices or space travel). Sometimes there is too little demand for fault-free ICs with extraordinary performance, resulting in a surplus. Such ICs may be sold in a lower price segment; sometimes their properties are not specifically restricted (e.g. a limitation of the clock rate). This allows the buyers of these ICs to achieve more power or lower energy consumption than is guaranteed according to the specification through overclocking or under-voltage operation. Here it is possible that completely different services can be achieved under the same trade name and at the same price. The uncertainty of possibly acquiring ICs with better performance than specified is seldom referred to as "silicon lottery".

Chiplet approach

Instead of monolithic ICs or SoCs, which combine all logic on one chip, the functions can also be distributed over several individual chips, so-called “chip sets” (miniaturization of chips). This reduces the size of the ICs to be manufactured and increases the likelihood of getting ICs manufactured without defects from production. Technically, this corresponds to the system-in-package approach. In the case of a monolithic chip with 360 mm², in the 7 nm production process, by dividing it into four individual chip sets, about double the theoretical yield can be achieved (this already takes into account the additional waste of about 10% for individual chip sets and a total area of ​​about 396 mm²) . In addition to the improved yield, individual chips can also be combined in different quantities or from different manufacturing processes on one package to form a respective product in order to obtain different end products. Above all, AMD processors such as Epyc , Threadripper and the Ryzen 3000 series rely on a chiplet design in which 1 to 8 chip sets (each with up to 8 active cores) are combined with an additional I / O die. Intel has also repeatedly produced CPU models (e.g. various Core 2 Quad models) from several chip sets in order to optimize production costs or yield.

literature

• John E. Ayers: Digital integrated circuits: analysis and design. Mcgraw-Hill Higher Education, 2003, ISBN 0-07-118164-4 , p. 31 ff.
• Gary S. May, SM Sze: Fundamentals of semiconductor fabrication . Wiley & Sons, 2004, ISBN 0-471-45238-6 , pp. 250 ff .

Web links

• How Many Squares (dies) Fit in a Circle (wafer)? Fab Revenue Simulation and Optimization ( Memento from September 30, 2015 in the Internet Archive )

Individual evidence

1. ^ Diebold, AC (Alain C.): Handbook of silicon semiconductor metrology . Marcel Dekker, New York 2001, ISBN 0-8247-0506-8 , pp. 537 ff .
2. ↑ ^{a b c} Gary S. May, SM Sze: Fundamentals of semiconductor fabrication . Wiley & Sons, 2004, ISBN 0-471-45238-6 , pp. 250 ff .
3. ↑ ^{a b} Manfred Kasper: microsystem design: design and simulation of microsystems . Springer, Berlin / Heidelberg 2000, ISBN 3-642-57123-9 , pp. 251 ff .
4. ↑ Christof Windeck: Infineon starts series production on 300 mm wafers . On: heise online. Dec 10, 2001.
5. ↑ Alexander Miczo: Digital logic testing and simulation . 2nd Edition. Wiley-Interscience, Hoboken, NJ 2003, ISBN 0-471-45777-9 , pp. 11 ff .
6. ↑ AMD Athlon II X4 Propus 600 Quad-Core Chips Include 45W Models. www.techPowerUp.com, July 10, 2009, accessed August 13, 2012 . 
7. ↑ What Is Binning? A basic definition. www.tomshardware.com, October 31, 2018, accessed September 5, 2019 . 
8. ↑ Chiplet. en.wikichip.org, June 21, 2019, accessed September 5, 2019 .