System-in-package

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System-in-Package ( SiP ) is an approach to integration in microelectronics , which technically between the monolithic On-chip integration ( System-on-a-chip , SoC) on a The (ungehauster semiconductor chip) and the on- Board integration of discrete components on a printed circuit board (PCB) or on a multi-chip module (MCM). Passive and active components as well as other components are combined in one housing (called IC package ) using microsystem technologies using assembly and connection technology . Related to SiP in structure are the Package-on-Package (PoP), in which various semiconductor chips are combined on top of one another.

General

In contrast to the multi-chip modules that have been manufactured for a long time, which are planar (i.e. two-dimensional) and thus belong to the electronic flat modules, the vertical integration of components can also be implemented in a SiP (3D, 2.5D SiP ) . The electrical connections between the individual dies are optionally substituted by bonding wires , as conductive thin films on side edges of this or via this the ( English through-silicon via executed TSV).

SoC and SiP represent two important manufacturing processes for complex integrated semiconductor components. With SiP, dies can be used that are based on different materials or have been manufactured with different process structures. In addition, discrete peripheral components can be integrated into the housing in a SiP. The production (packaging) of the SiP is more expensive than the SoC, while the complete integration of all functionalities on one chip is usually more expensive. Which variant is cheaper depends very much on the functionality of the circuit.

There is design software available from the major EDA providers for designing SiPs . With SiP, it makes economic sense to use known good die tests to check that the chips are free of defects before integration.

Related approaches

Flip chip assembly

Individual evidence

↑ ^a ^b R. Fischbach, et al .: From 3D Circuit Technologies and Data Structures to Interconnect Prediction . In: Proc. of 2009 Int. Workshop on System Level Interconnect Prediction (SLIP) . 2009, p. 77-83 , doi : 10.1145 / 1572471.1572485 ( PDF ).
↑ J. Lienig, M. Dietrich (Ed.): Design of integrated 3D systems in electronics. Springer, 2012, pp. 10-11, ISBN 978-3-642-30571-9 .

[Fischbach-1] R. Fischbach, et al .: From 3D Circuit Technologies and Data Structures to Interconnect Prediction . In: Proc. of 2009 Int. Workshop on System Level Interconnect Prediction (SLIP) . 2009, p. 77-83 , doi : 10.1145 / 1572471.1572485 ( PDF ).

[LieDie-2] J. Lienig, M. Dietrich (Ed.): Design of integrated 3D systems in electronics. Springer, 2012, pp. 10-11, ISBN 978-3-642-30571-9 .