Package-on-Package

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PoP using the example of the Raspberry Pi single-board computer . Above is the memory chip in the black housing, between the motherboard and memory the BGA chip of the ARM processor chip with integrated graphics processor can be seen .

Package-on-Package ( PoP , literally translated as "housing on housing") isa manufacturing technologyin the assembly and connection technology of microelectronics in which two or more specially prepared chip housings , usually ball grid arrays (BGA) , assembled one on top of the otherandsolderedonto the circuit board in this stacked arrangement. This design allows a higher integration density than the arrangement of the individual BGA housings next to one another on the circuit board and is preferably used in smartphones , digital cameras and tablet computers . PoP wasdevelopedby Maxim Integrated Products in 2007and the type of structure isspecifiedin JEDEC standards.

General

In the case of package-on-package with two individual housings, the lower BGA must have connection pins on both sides. As with all BGA housings, balls are soldered down to the motherboard , and up to the upper BGA housing there are corresponding soldering surfaces for receiving the connection pins from the upper BGA housing. The two BGA housings are manufactured separately and only fitted on top of each other using automatic placement machines on the circuit board immediately before the reflow soldering process . Since during the soldering process the heat has to pass through the upper BGA chip to the lower BGA chip in order to securely solder the lower BGA connection pins to the motherboard, on the other hand no damage due to excess temperature may occur in the semiconductor chips Correspondingly precise and coordinated temperature profiles are required for the soldering process.

PoP is typically used in two areas:

  • With two or more memory chips. Usually these are highly integrated DDR-SDRAM memories. Applications are in compact memory cards or memory modules.
  • The combination of a main processor (CPU) in the lower chip and above it the main memory required for the system-on-a-chip (SoC) , usually designed as DDR-SDRAM . This combination is used in mobile computer systems and is shown schematically in the following sectional illustration.
Schematic sectional view of a PoP consisting of the main processor located below and above the chip housing with the main memory

Package-on-package is to be distinguished from the so-called system-in-package (stacked-die-package), in which two or more dies , i.e. the unhoused semiconductor chips, are accommodated in a chip housing and appear to the outside like a single chip . System-in-package are used, among other things, for flash memories in order to be able to increase the storage capacity per chip housing.

One advantage of package-on-package over system-in-package is that the individual chips can be tested separately before they are fitted. In principle, it is also possible to define a specific chip combination until shortly before the soldering process. With package-on-package, the memory chip on top can be varied in memory size before the soldering process. One advantage of PoP over printed circuit boards is the short conductor paths between the two chips. This means that the memory and the connection between the two chips can be operated at high clock frequencies .

The disadvantage of PoP is the comparatively poor possibility of being able to dissipate waste heat into the environment by means of a heat sink during operation . The lower chip, in particular, has a hard time giving off its waste heat. Therefore, PoP is primarily limited to applications where there is only a low power loss and a comparatively low power consumption. This is typically the case with mobile electronic devices such as smartphones or tablet computers.

Web links

Commons : PoP integrated circuit packages  - collection of images, videos and audio files

Individual evidence

  1. ↑ JEDEC Standard No. 21-C , pages 3.12.2 - 1
  2. ↑ Patent US7923830 : package-on-package secure module having anti-tamper mesh in the substrates of the upper package. Filed April 13, 2007 , published April 12, 2011 , Inventors: Steven M. Pope, Ruben C. Zeta. ‌
  3. ↑ a b R. Fischbach, et al .: From 3D Circuit Technologies and Data Structures to Interconnect Prediction . In: Proc. of 2009 Int. Workshop on System Level Interconnect Prediction (SLIP) . 2009, p. 77-83 , doi : 10.1145 / 1572471.1572485 ( PDF ).