Silicon via

Stacked DRAM dice use TSVs, here with an HBM memory interface.

By the term silicon via ( English through-silicon via , TSV) is understood in the semiconductor art , a generally vertical electrical connection of metal by a silicon - substrate ( wafer , chip ). TSV technology is a promising way of realizing electrical connections between partial chips in the 3D integration of future integrated circuits (IC).

Classification

Visualization (from left to right) of via-first, via-middle and via-last TSVs

Due to the manufacturing process, TSVs can be divided into three classes: Via-first TSVs are processed in front of the active components ( transistors , etc., also referred to as front-end of line , FEOL). Via-middle TSVs are structured according to the active components, but before they are wired (metallization, also known as back-end of line , BEOL). Via-last TSVs are finally implemented after (or during) the application of the wiring metallization, i.e. the BEOL.

Via-middle TSVs are currently the most widely used variant for modern 3D ICs as well as for interposer structures.

Process technology

Challenges include the final inspection of the partial chips after packaging in the case of 3D integration. Usually a chip is placed on a chip carrier and the final test for the end customer is carried out after bonding . In the case of 3D integrated chips the z. If silicon vias are used, for example, only the 3-D chip could be tested, since the interfaces of the circuits on the partial chips are usually not routed to the outside. Thus, ways must be found to carry out the final test for the partial chips in good time or the evaluations must be limited to the results of the last electrical test at the end of the BEOL process (before the bump and the dicing of the wafer).

application

A 3D integrated circuit (3D IC) is an integrated circuit that consists of a vertical stack of individual thinned chips. It appears to the outside like a monolithic circuit, but strictly speaking it is more of a hybrid circuit that is much more integrated than typical hybrid circuits. Overall, one would like to achieve an even higher functionality of the ICs with the same housing base area with this 3D integration. The through-hole plating with the help of TSVs connects the individual chip levels in the 3D IC. TSV is currently the most promising technology for realizing the high requirements (short, robust, etc.) on the electrical paths.

Another application is so-called 3D housings ( system-in-package , multi-chip module, etc.). They contain two or more ICs that are stacked vertically to save space. An alternative variant of a 3D housing is IBM's " Silicon Carrier Packaging Technology ", in which the ICs are not stacked, but a carrier substrate is provided with TSVs and is used to connect several ICs in one housing. Unlike most 3D packages, the stacked chips are therefore not wired through electrical connections on the sides; Wiring technology increases the length and width of the package somewhat and usually requires an additional layer of " interposer " between the chips. When wiring via TSVs, this wiring was exchanged for vias on the sides in order to produce the vertical connections distributed over the chip area. The main advantages are more robust connections and even lower heights. The loss of chip area due to the additional TSVs can be disadvantageous. This technique is sometimes referred to as through-silicon stacking or thru-silicon stacking (TSS).

swell

Applied Materials Leads the Way to Enable TSV Interconnects for 3D Chip Stacking . Business Wire, July 12, 2010 (Applied Materials press release)

literature

Vasilis F. Pavlidis, Eby G. Friedman: Three-dimensional integrated circuit design . Morgan Kaufmann, 2009, ISBN 978-0-12-374343-5 , pp. 48 ff . ( limited preview in the Google book search - the book contains descriptive images of TSV as well as good images of the other 3D integration methods).

Web links

Through-Silicon Via 3D Integration (PDF; 86 kB). Applied Materials, January 25, 2010.

Individual evidence

↑ ^a ^b J. Knechtel, et al .: Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration . In: IPSJ Transactions on System LSI Design Methodology . 10, 2017, pp. 45-62. doi : 10.2197 / ipsjtsldm.10.45 .
↑ J. Lienig, M. Dietrich (Ed.): Design of integrated 3D systems in electronics. Springer, 2012, pp. 11, 147, ISBN 978-3-642-30571-9 .
^ E. Beyne: The 3-D Interconnect Technology Landscape . In: IEEE Design Test . 33, No. 3, June 2016, ISSN 2168-2356 , pp. 8-20. doi : 10.1109 / mdat.2016.2544837 .
^ Through-Si Via (TSV), 3D Stacking Technology . In: International Technology Roadmap for Semiconductors 2009 Edition. Interconnect . 2009, p. 37-42 ( PDF ).

[3D-1] J. Knechtel, et al .: Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration . In: IPSJ Transactions on System LSI Design Methodology . 10, 2017, pp. 45-62. doi : 10.2197 / ipsjtsldm.10.45 .

[LieDie-2] J. Lienig, M. Dietrich (Ed.): Design of integrated 3D systems in electronics. Springer, 2012, pp. 11, 147, ISBN 978-3-642-30571-9 .

[3] E. Beyne: The 3-D Interconnect Technology Landscape . In: IEEE Design Test . 33, No. 3, June 2016, ISSN 2168-2356 , pp. 8-20. doi : 10.1109 / mdat.2016.2544837 .

[4] Through-Si Via (TSV), 3D Stacking Technology . In: International Technology Roadmap for Semiconductors 2009 Edition. Interconnect . 2009, p. 37-42 ( PDF ).