3D integration

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Among 3D integration is understood in the electronics an integrated circuit (IC, chip) in which the active electronic components including vertically in two or more layers, both horizontally integrated are, that is, connected to a single circuit, a so-called dreidimensional- integrated circuit (3D IC). Vertical connections between different active levels are made possible by silicon vias ( through-silicon vias ). In the semiconductor industry, 3D integration is traded as a promising way to continue the trend towards more compact and powerful electronic devices (“More than Moore ”); different approaches are being pursued.

Difference between 3D ICs and 3D packaging

Example of the 3D integration of a main chip and three secondary chips

3D Packaging (engl. 3D packaging ) saves space by stacking of individual chips in a single housing. In this technology, also known as system-in-package (SiP) or chip-stack multi-chip modules , the individual ICs are not integrated in a single circuit. They continue to communicate outside the chip via electrical signals, just as if they were mounted in different housings on a circuit board . In contrast, a 3D IC acts like a single IC. All components on all chip levels communicate with each other within the 3D IC, depending on how it was designed, vertically as well as horizontally. A 3D-IC therefore behaves in a similar way to 3D packaging as a system-on-a-chip does to a printed circuit board.

Manufacturing techniques

The four most common ways to fabricate 3D integrated circuits are listed below:

Monolithic manufacturing
The electronic components and their connections (the wiring) are applied in layers to a single semiconductor substrate (wafer), which is then divided into individual chips. Since there is only a single substrate, there is no need to align, bond, or via individual chips. Applications of this method are currently still limited because the production of normal transistors requires very high process temperatures, which means that electrical lines that have already been manufactured could be destroyed or damaged. This monolithic 3D IC technology was researched at Stanford University as part of a DARPA- funded donation
Wafer-on-Wafer method
The electronic components are built on two or more semiconductor substrates (wafers), which are then aligned and bonded. Finally, the bonded wafers are separated into the 3D ICs. The wafer can be thinned before or after the bonding. Vertical electrical connections (vias) can also either be made in the chips before bonding or after the stack has been produced. These silicon vias ( through-silicon via , TSV) can run through single or multiple substrates and connect active layers to one another or to an external bond pad. The advantage of this method is the relatively low workload, since all ICs on the substrates are connected to one another in parallel. The wafer-on-wafer method can reduce the yield more, because if only one of the n partial chips in a 3D IC is defective, the entire 3D IC will be defective. Individual bonding errors can even make all 3D IC unusable. In addition, the wafers must be of the same size, but with many exotic materials (e.g. III-V semiconductors ) the wafers are significantly smaller (usually max. 100 mm wafers) than with silicon wafers for CMOS logic or DRAM (typically 300 mm wafers), which makes such heterogeneous 3D integrations difficult or impossible.
The-on-wafer method
The electronic components are built on two different semiconductor substrates. One of these substrates is separated into its chips. The individual chips are then aligned and bonded to the chips of the other substrate. As with wafer-on-wafer technology, the thinning of the wafers and the production of vias can be carried out either before or after the bonding. Furthermore, additional chips can be integrated into the stack before the final separation of the 3D ICs.
The-on-the- method
The electronic components are built on two or more semiconductor substrates, the partial chips are then separated, aligned with one another and bonded. The thinning of the partial chips and the production of plated-through holes can in turn take place before or after the bonding. A major advantage of this method is that each partial chip can first be tested individually so that defective components can be discovered and sorted out at an early stage. In this way, it can be better prevented that a single defective chip prevents the function of the finished 3D IC. In addition, each partial chip of the 3D IC can be characterized beforehand so that they can be optimally mixed and matched to one another with regard to power consumption and performance, for example for mobile use with particularly low power consumption.

advantages

The traditional scaling of semiconductor chips also improves signal delay. However, the further scaling of current manufacturing and chip design technologies has become more difficult, on the one hand because of the restrictions with regard to the maximum power density and on the other hand because the electrical connections, unlike the transistors, have not become faster themselves. For this reason, 3D integrated circuits have been proposed to address the challenges of further scaling by stacking traditional 2D integrated circuits and connecting in the third dimension. This promises to speed up communication compared to a planar arrangement. There are many important advantages associated with 3D ICs, including:

  • Smaller footprint: With 3D ICs, more functional components fit on a smaller area of ​​the component carrier, e.g. B. on the circuit board. This enables new generations of small but powerful devices.
  • Lower costs: The die size and the achievable minimum defect density limit the theoretically maximum achievable yield of integrated circuits. Therefore, dividing larger 2D ICs into several smaller sub-chips and stacking them in 3D ICs can increase the yield and thus reduce manufacturing costs. This is especially true if the partial chips were individually tested for their function before bonding. The cost advantage therefore applies less to the wafer-on-wafer method.
  • heterogeneous integration: 3D ICs offer the possibility of integrating partial chips from different manufacturing processes. This makes it possible to optimize the production of the individual components to a much higher degree than if they are produced together on one chip. In addition, it means that components from different and incompatible manufacturing techniques can be assembled in a 3D IC.
  • Shorter signal paths and lower power consumption: The reduction in power consumption generally leads to an increase in battery life. Furthermore, less waste heat is generated as a result, which leads to low requirements for cooling and in turn enables smaller devices. It should be noted, however, that the heat dissipation tends to deteriorate due to the stacking, so that with 3D ICs the power consumption generally has to be lower and more attention should generally be paid to the occurrence of local heat centers. In addition to the general reduction of supply voltages during scaling, with 3D-Ics a lower power consumption is achieved through shorter signal paths. The power consumption for signals that now remain on the chip can be reduced by a factor of 10–100. Shorter electrical connections also reduce the required power consumption, since fewer parasitic capacitances occur.
  • Design / structure: The use of an additional dimension enables a higher order in the connectivity of the components and thus new possibilities in structure and design.
  • Bandwidth: The 3D integration allows a large number of vertical connections between the individual chip levels. This enables broadband data buses to be established between functional blocks in different levels. A typical example of this would be a processor and memory stack with the cache memory placed above the processor. This arrangement allows buses with much greater bandwidth than current typical 128 or 256 bit buses. Large buses, on the other hand, alleviate the memory wall problem , that is, the fact that today's processors often have to wait for memory access and thus cannot utilize their actual performance.

Challenges

Because this technique is new, it also has new challenges to overcome, including:

  1. Yield: Each additional production step increases the risk of additional defects. In order for 3D ICs to be successfully implemented commercially despite the tendency towards higher defect rates, defects could be tolerated or repaired / improved. Overall, however, as with any technology, the defect density must be reduced so that its use is commercially viable.
  2. Heat development and dissipation : The heat loss that occurs in the chip must be dissipated within the stack. Thermal hotspots in particular must be carefully considered.
  3. Design Complexity: Taking full advantage of 3D integration requires sophisticated design techniques and new CAD tools.
  4. TSV-induced overhead: Compared to gate structures, TSVs are large and affect the circuit layout. At the 45 nm technology node, a TSV takes up approximately the area of ​​10 µm², which corresponds to the area of ​​approx. 50 gate structures. In addition, additional space is required for the placement area and the surrounding restricted zones for other IC components, which further increase the space requirements of TSVs. Depending on the technology chosen, TSVs block some of the layout resources. Via-first TSVs are manufactured before metallization, so they occupy the transistor level and lead to placement barriers. In contrast, with via-last TSVs, the TSVs are manufactured after metallization and go through the chip. They thus occupy both the transistor and the metallization levels , which leads to placement and routing obstacles. While the use of TSVs is generally associated with reducing the signal line length, in reality this depends on the number of TSVs and their properties. In addition, the granularity of the block division on the sub-chips affects the line length. As a rule, it decreases for moderate (blocks with 20 to 100 modules) and coarse (block-level division) granularities, but increases for fine (gate-level division) granularities.
  5. Testing the circuit: In order to achieve a high overall yield and reduce costs, separate tests of the independent partial chips are essential. However, the close integration between adjacent active layers in a 3D IC entails a significant amount of signal connections between the different parts of the same circuit module that has been split between different sub-chips. Apart from the massive overhead introduced by the vias required, the parts of such a module, e.g. B. a multiplier, cannot be tested independently of conventional techniques. This is especially true for time-critical paths.
  6. Lack of standards: Currently there are few standards for TSV-based 3D IC designs, their manufacture and packaging, although these issues are already addressed. In addition, there are many integration options that are currently being explored, e.g. B. the approaches via-last (TSV production after the metallization levels), via-first (TSV production before metallization) and via-middle (production parallel to metallization), interposer , direct bonding etc.
  7. Supply chain in heterogeneous integration: In heterogeneously integrated systems, the delivery delay of a component from one of several component suppliers is decisive for the delays of the entire product, and so the revenue for each of the suppliers involved for the 3D IC is delayed.

Design methods

Depending on the division of the function blocks to the individual sub-chips, a distinction can be made between two design methods: gate-level and block-level integration. Gate-level integration is faced with a variety of challenges and currently seems less practical than block-level integration.

Gate level integration

When integrating the circuit at gate or transistor level, the standard cells (function blocks) are divided into several sub-chips. This integration variant promises a shortening of the cable routes and great flexibility. However, the advantage of shorter cable routes only comes into play if the sub-function blocks do not fall below a certain size. On the other hand, there is the high number of vias required for the connections between the sub-chips. A large number of vias takes up expensive chip area and increases the complexity of the design. Gate-level integration requires 3D place-and-route software, which is not currently available. Furthermore, the division of a function block over several partial chips implies that the blocks cannot be fully tested before the 3D IC is assembled. The failure of an area on a partial chip can cause the failure of the entire 3D IC and thus several good partial chips, which further reduces the yield. In addition, this method also increases the influence of process variations, in particular variation between partial chips. Therefore, the yield can be lower with a 3D layout than with a 2D IC of the same circuit. Furthermore, the gate-level integration forces a redesign of existing designs, since above all existing IP cores and EDA software are currently not available for the 3D integration.

Block level integration

With this method, only complete function blocks are distributed to the individual chips. The function blocks mostly contain the majority of the conductor track network and are linked to one another via a small number of "global" connections. For this reason, block-level integration promises a reduction in excess vias. Demanding 3D systems, in which heterogeneous individual chips are combined with one another, require different manufacturing processes at different technology nodes for fast or energy-saving logic, different memory types, analog and HF circuits etc. Therefore, the block-level integration seems to be the separate and optimized manufacturing process enables, crucial for the success of a 3D integration. In addition, this technology can facilitate the transition from current 2D to 3D IC design. Basically, 3D-capable software tools are only necessary for dividing the function blocks onto the individual chips and for thermal analysis. The respective individual chips can be developed with existing (possibly adapted) 2D tools and 2D blocks. This benefits from the wide availability of reliable IP cores, as it is easier to use available 2D IP cores and place the mandatory vias in the free space between the blocks, instead of redesigning the IP blocks and embedding vias in them. Design-for-testability structures are an integral part of the IP blocks and can therefore be used to facilitate testing for 3D ICs. In addition, many critical paths can be built into the 2D blocks, which limits the impact on the yield due to variations in the production of the vias and between the individual chips.

Notable 3D ICs

Presented in 2004 Intel a 3D version of its Pentium 4 - CPU . The stacked chip was made from two individual chips, with the side with the active components facing each other and connected, which allows a dense via structure. Vias on the back of the individual chips were used for the external signal connection and the power supply. For the layout and wiring diagram in 3D, the designers manually arranged the functional blocks of each chip with the aim of reducing and improving performance. The division of large and high-performance blocks as well as careful rearrangement allow thermal hotspots to be limited. Compared to the 2D Pentium-4, the 3D design enabled an increase in performance of 15% (due to removed pipeline stages) and energy savings of 15% (due to removed repeaters and reduced wiring).

The Teraflop research chip was introduced by Intel in 2007 and is an experimental 80-core design with stacked memory units. Due to the high demand for memory bandwidth, a traditional IO approach would require 10-25W. In order to achieve an improvement to the Intel designers have an on -silicon (Engl. Through silicon via , TSV) based memory implemented. Each core is connected to a memory level of the SRAM chip via a 12 GB / s connection. This results in a total bandwidth of 1 TB / s and requires only 2.2 W.

A more academic implementation of a 3D processor was presented in 2008 by staff and students working with Professor Eby Friedman at the University of Rochester . The circuit runs at a clock frequency of 1.4 GHz and was designed for optimized vertical processing between the stacked chips, which should give the 3D processor capabilities that a traditional circuit in one plane could not achieve. A challenge in the production of the three-dimensional circuit was that all levels work harmoniously and undisturbed, without any information that is exchanged between the individual levels interfering with one another.

Simulators

IntSim is an open source CAD program that can be used to simulate 2D and 3D ICs. It can also be used to predict the performance, size, number of wiring levels and the optimal size of the wiring levels of 2D / 3D chips based on different techniques and design parameters. Users can also study scaling trends and use the program to optimize their chip designs.

Further material and sources

literature

Miscellaneous

Possible applications

Web links

Selected press articles

Individual evidence

  1. ^ Applications of Monolithic 3D . MonolithIC 3D Inc.
  2. ↑ 3D Integration: A Revolution in Design . Real World Technologies, May 2, 2007.
  3. ↑ 3D Processors, Stacking Core . Developer Shed. September 20, 2005, page 1.
  4. ↑ 3D Processors, Stacking Core . Developer Shed. September 20, 2005, page 2.
  5. ↑ Xiangyu Dong Yuan Xie: System-level Cost Analysis and Design Exploration for 3D ICs. In: Proceedings of Asia and South Pacific Design Automation Conference, 2009. 3A-1 ( PDF ( Memento of April 6, 2012 in the Internet Archive )).
  6. ^ Roger Allen: 3D IC Technology Delivers The Total Package ( Memento from October 31, 2010 in the Internet Archive ). IN: Electronic Design. July 2, 2010.
  7. ↑ James J.-Q. Lu, Ken Rose, Susan Vitkavage: 3D Integration: Why, What, Who, When? ( Memento from February 12, 2008 in the Internet Archive ) In: Future Fab International. Volume 23, 2007 ( PDF ).
  8. ^ William J. Dally: Future Directions for On-Chip Interconnection Networks. OCIN workshop, December 7, 2006 ( presentation slides as PDF ).
  9. ^ R. Colin Johnson: 3-D chip stacks standardized . July 10, 2008.
  10. ↑ Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, Hsien-Hsin S. Lee: An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth . In: 2010 IEEE 16th International Symposium on High Performance Computer Architecture (HPCA) . IEEE, 2010, ISBN 978-1-4244-5658-1 , pp. 1–12 , doi : 10.1109 / HPCA.2010.5416628 .
  11. ^ P. Jacob, O. Erdogan, A. Zia, P. M Belemjian, R. P Kraft, J. F McDonald: Predicting the performance of a 3D processor-memory chip stack . In: IEEE Design & Test of Computers . tape 22 , no. 6 , 2005, p. 540-547 , doi : 10.1109 / MDT.2005.151 .
  12. ^ Robert Patti: Impact of Wafer-Level 3D Stacking on the Yield of ICs ( Memento of May 17, 2014 in the Internet Archive ). In: Future Fab Intl. Volume 23, 2007
  13. ↑ EDA's big three unready for 3D chip packaging ( Memento of the original from July 18, 2008 in the Internet Archive ) Info: The @1@ 2Template: Webachiv / IABot / www.eetasia.com archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. . EE Times Asia, October 25, 2007.
  14. ↑ a b c d Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim: Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs . In: Proceedings of the 11th international workshop on System level interconnect prediction . ACM, New York, NY, USA 2009, ISBN 978-1-60558-576-5 , pp. 85-92 , doi : 10.1145 / 1572471.1572486 .
  15. ↑ a b S. Borkar: 3D integration for energy efficient system design . In: Proceedings of the 48th ACM / EDAC / IEEE Design Automation Conference (DAC) . IEEE, 2011, ISBN 978-1-4503-0636-2 , pp. 214-219 .
  16. ↑ H.-HS Lee, K. Chakrabarty: Test Challenges for 3D Integrated Circuits . In: IEEE Design & Test of Computers . tape 26 , no. 5 , 2009, p. 26-35 , doi : 10.1109 / MDT.2009.125 .
  17. ↑ 3-D chip stacks standardized . EE Times November 7, 2008.
  18. ↑ SEMI International Standards Program Forms 3D Stacked IC Standards Committee ( Memento of the original from May 17, 2014 in the Internet Archive ) Info: The @1@ 2Template: Webachiv / IABot / www.semi.org archive link has been inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. . SEMI, December 7, 2010 (press release).
  19. ↑ ADVANCED PACKAGING: 3D TSV Technologies Scenarios: Via First or Via Last? 2010 report ( Memento from May 17, 2014 in the Internet Archive ). Yole report, 2010.
  20. ^ Si, glass interposers for 3D packaging: analysts' takes ( Memento from July 22, 2012 in the Internet Archive ). Advanced Packaging August 10, 2010.
  21. ↑ a b J. Knechtel, IL Markov, J. Lienig: Assembling 2D blocks into 3D chips . In: Proc. of the 2011 Int. Symp. On Physical Design . ACM, New York, NY, USA 2011, ISBN 978-1-4503-0550-1 , pp. 81-88 , doi : 10.1145 / 1960397.1960417 . See also: J. Knechtel, IL Markov, J. Lienig: Assembling 2-D Blocks Into 3-D Chips . In: IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems . tape 31 , no. 2 , 2012, p. 228–241 , doi : 10.1109 / TCAD.2011.2174640 ( PDF ).
  22. ↑ a b J. Lienig, M. Dietrich (Ed.): Design of integrated 3D systems in electronics. Springer, 2012, ISBN 978-3-642-30571-9 .
  23. ↑ S. Garg, D. Marculescu: 3D GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs . In: Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design . IEEE, 2009, ISBN 978-1-4244-2952-3 , pp. 147–155 , doi : 10.1109 / ISQED.2009.4810285 .
  24. ^ LK Scheffer: CAD implications of new interconnect technologies . In: Proc. of the 44th Annual Design Automation Conf. ACM, New York, NY, USA 2007, ISBN 978-1-59593-627-1 , pp. 576-581 , doi : 10.1145 / 1278480.1278626 .
  25. ^ B. Black, D. W Nelson, C. Webb, N. Samra: 3D processing technology and its impact on iA32 microprocessors . In: IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings . IEEE, 2004, ISBN 0-7695-2231-9 , pp. 316-318 , doi : 10.1109 / ICCD.2004.1347939 .
  26. ↑ Steve Seguin: World's First Stacked 3D Processor Created . September 16, 2008.
  27. ↑ 3-D Computer Processor: 'Rochester Cube' Points Way To More Powerful Chip Designs . Science Daily, September 17, 2008.
  28. ↑ IntSim . MonolithIC 3D Inc.
  29. ↑ Peter Clarke: Monolithic 3D offers IC power simulator . eetimes.com, June 8, 2011