Defect (semiconductor technology)

In semiconductor technology, defects are generally undesired, local defects in the manufacture of semiconductor products. They generally reduce the quality and reliability of the products and can cause them to fail completely. Defects are often given in the form of the defect density D , the number of defects per unit area , or the defect density per lithographic mask plane.

Type, cause and effect

The type, cause and effect of defects that occur in the manufacture of semiconductor products are very diverse. They range from particles of all kinds to crystal defects in the substrate or epitaxial layers to defects caused by incorrect processing in photolithography or etching. The defects can come from the environment (e.g. dust) or arise from the manufacturing processes (e.g. material residues , overlay offset ) themselves. As a rule, they have a mechanical or electrical influence, for example on the reliability or the quality (e.g. achievable clock frequency ) of the chips. However, they can also lead to electrical failure or malfunction and even destruction of the product. Such so-called "fatal" defects affect the yield (Engl. Yield ) of microelectronic products.

In the following some typical examples of defects from different areas of production are named and their possible effects are briefly described.

Probably the most well-known defects are particles from the environment in which the wafers are transported and processed, and the systems themselves. These include, for example, dust and material abrasion. Such particles can (temporarily) accumulate on the wafer and lead to undesirable coverage there. There they can locally influence the processing in the affected area, for example by preventing the deposition or the etching of layers, or they cause undesired topographical obstacles (e.g. focus problems in photolithography, layer deposition of the photoresist). The result is, for example, an electrical malfunction in the form of short circuits or missing electrical connections between conductor tracks . Such particles from the environment can be viewed as a kind of basic defect load, which can be largely reduced by a correspondingly clean environment (see clean room class ) and suitable material selection (see clean room suitability ) and construction. Nevertheless, they represent a large part of the defects relevant to exploitation . The rule of thumb for the size of particles relevant to exploitation is that it should not exceed 25% or 10% of the structure size. The requirements for the reduction of defects therefore increase as the integration density of integrated circuits increases .

Contamination by foreign materials can also negatively affect the function of the products, for example metal ions that diffuse into electrically sensitive areas such as the transistor channel and change the electrical properties there.

Many other sources of defects have process engineering causes. This is understood to mean defects that result from non-optimized manufacturing processes. In general, these are individually controllable process fluctuations which, however, cannot be avoided, especially in high-volume production, for example:

Deposition problems that cause voids in thin layers or in contact holes ( pin holes ), but also air bubbles when the photoresist is applied
Adhesion problems of layers, for example due to excessive temperature fluctuations and the resulting mechanical stress
Material residues, for example after chemical-mechanical planarization
Crystal defects in the substrate or epitaxial layers, for example stacking faults, impurities, mechanical stress, etc.
Overlay errors that cause undesired connections between different levels (e.g. short circuits) or prevent desired connections (e.g. lack of electrical contact between conductor tracks)
and much more.

In addition, there are “gross” defects such as scratches, most of which are the result of system or handling errors, as well as technological sources of defects. The latter are usually not optimized process sequences and interactions between the manufacturing steps. For example, excessively high temperatures can lead to mechanical stress in existing thin layers, which in turn leads to fractures in the material. These break points can, for example, increase the electrical resistance of metal layers or be a diffusion path for water or metal ions in dielectric layers.

Meaning: Influence on the yield

Three examples of the change in the yield on a 300 mm wafer depending on the die size (top: 10 mm × 10 mm; center: 20 mm × 20 mm; bottom: 40 mm × 40 mm). With the same, evenly distributed number of defects (red point), the number of defective chips (yellow) is reduced and the yields are 94.2%, 75.7% and 35.7%, respectively.

The number of defects on a wafer or the defect density is determined together with the chip size significantly the attainable yield ( English yield ) of usable chips per wafer. It should be noted here that with an increasing degree of integration, even smaller defects, which in larger structures did not yet cause the circuit to fail, now represent fatal defects. This means that the general defect density during production must decrease with the degree of integration in order to be able to achieve a sufficient yield. This is all the more important since the degree of integration often goes hand in hand with a higher number of processing steps, and therefore more defects tend to occur.

If one looks at the course of the defect density occurring during production for a manufacturing technology or for a product, the defect density of the first prototypes is usually very high, so that they often show only a very small number or no fully functional chips. Through constant learning processes and the improvement of the individual production steps, the number of technologically-related defects is then rapidly reduced.

For the calculation, simple models assume a uniform distribution of the defect density over the wafer ( Poisson model ):

{\ displaystyle Y = e ^ {- A \ cdot D}}

with the yield , the chip area and the defect density . According to this very simple model, the fatal defect density for a 250 mm² chip would have to be 0.25 defects per square centimeter and below in order to obtain economic yields of over 50%. ${\ displaystyle Y}$ ${\ displaystyle A}$ ${\ displaystyle D}$

As a rule, however, this model is only suitable for calculating the yield for large wafer quantities, since here the fluctuations from wafer to wafer and on the wafer itself can be averaged. In reality, the defect density on a wafer fluctuates, that is, there are areas with very low defect rates and areas with very high defect rates can exist (defect clusters ). This defect density distribution is usually not the same from wafer to wafer or lot to lot. Examples of such defect clustering are often systematic system influences such as a fluctuation in the planarization quality (cf. chemical-mechanical planarization , CMP) over the radius. Such an unevenly distributed defect density can have a very great influence on the yield, since more defects occur on a chip with the same number of defects, but the number of chips affected overall decreases.

Individual evidence

^ Gary S. May, Simon M. Sze: Fundamentals of Semiconductor Fabrication . International ed. Wiley & Sons, 2003, ISBN 0-471-45238-6 , pp. 60-62 .
↑ Gerhard Kienel: vacuum coating: Volume 4: Applications . Springer DE, 1997, ISBN 978-3-540-62274-1 , pp. 165 .
↑ Dietrich Widmann, Hermann Mader, Hans Friedrich: Technology of highly integrated circuits . Springer, 1996, ISBN 978-3-540-59357-7 , pp. 256 .

[1] Gary S. May, Simon M. Sze: Fundamentals of Semiconductor Fabrication . International ed. Wiley & Sons, 2003, ISBN 0-471-45238-6 , pp. 60-62 .

[2] Gerhard Kienel: vacuum coating: Volume 4: Applications . Springer DE, 1997, ISBN 978-3-540-62274-1 , pp. 165 .

[3] Dietrich Widmann, Hermann Mader, Hans Friedrich: Technology of highly integrated circuits . Springer, 1996, ISBN 978-3-540-59357-7 , pp. 256 .