Layout synthesis
Under layout synthesis is understood to automate the creation of the geometrical arrangement of the cells and their compounds in the layout design of an integrated circuit . The input information is the network list created in the circuit design as well as library information on the cells and technology information. The result of the layout synthesis is the graphic, level-specific mapping of all elements of the circuit, often in the GDSII or OASIS file format.
description
In the case of layout synthesis, the network list of a circuit is converted into its real geometric representation using library and technology information. All circuit elements (cells / gates, macro cells, transistors, etc.) are shown in their geometric image (shape, dimensions, level assignment) and their spatial arrangement (placement) and the specific connection structures (wiring) between them are determined. The result is the layout of the circuit, which z. B. is transferred level-specific to masks after their verification and thus enables the production of an integrated circuit.
The layout synthesis always takes place with the inclusion of technology information, which, as so-called design rules, enable the technology-correct layout to be created. For example, the minimum conductor track widths must be known before they can be arranged. The design rules are derived from the limit values of the technological implementation process and the electrical properties of the material used. Due to the inclusion of technology information, layout synthesis is also the first step in which the design of digital circuits becomes technology-dependent. This has specific implications for technology transformation. H. The transfer of a tried and tested circuit to a new technology: Here, the steps before the layout synthesis do not usually have to be carried out again. Only the layout synthesis and the following steps need to be processed again using the new technology information and thus also including a modified cell library.
procedure
Due to its complexity, the layout synthesis is divided into individual sections. In digital chip design you can e.g. B. apply the following steps:
- Partitioning - dividing a circuit into sub-circuits or circuit blocks that can be designed individually
- Floorplanning - definition of the shapes and the arrangement of the circuit blocks as well as the assignment of their external connections
- Wiring of the power supply and ground networks - distribution of power supply (Vdd) and ground network (Gnd) over the chip area
- Placement - Exact arrangement of all cells in a circuit block
- Wiring of the clock networks (clock tree synthesis) - definition of the layout of the clock networks and any necessary amplifiers (buffers)
- Global wiring - global assignment of the individual signal networks to wiring regions
- Fine wiring - Exact embedding of the signal networks on tracks and layers within the already assigned wiring regions
- Compacting or timing closure - optimization of the layout area or other circuit parameters.
Layout synthesis in analog design
In the analog design of integrated circuits, the generation of the geometric image of a circuit element defined in the circuit diagram is often carried out using so-called (layout) generators. These are automatically able to derive its geometric representation (e.g. length and width on a certain level) based on the electrical properties assigned to the circuit element (e.g. a resistor) in the circuit diagram (e.g. the resistance value) ).
See also
literature
- J. Lienig: Layout Synthesis of Electronic Circuits - Basic Algorithms for Design Automation ; 2nd edition, Springer (2016), Berlin, Heidelberg, New York, ISBN 978-36-624-9814-9 .
- V. Meyer zu Bexten: User-Controlled Layout Synthesis for Analog Integrated Circuits ; Shaker (1994), Aachen, ISBN 3-8265-0093-8 .
- A. Kahng, J. Lienig, I. Markov, J. Hu: VLSI Physical Design: From Graph Partitioning to Timing Closure ; Springer (2011), Berlin, Heidelberg, New York, ISBN 978-90-481-9590-9 .