Semiconductor technology
The Semiconductor Technology ( HLT ) is a technical department that deals with the design and manufacture of products based on semiconductor materials employed, especially microelectronic assemblies (eg. As integrated circuits ). It defines itself historically and due to the use of the products as key components in electrical engineering products as a sub-area of electrical engineering (especially microelectronics and nanoelectronics ). If the assignment is made based on the methods and processes used and the material properties of the manufactured products, an assignment to the areas of chemical engineering and ceramics is possible and consistent.
Related or derived specialist areas are microsystem technology and photovoltaics . Both also use methods of semiconductor technology, initially do not contain any microelectronic circuits. The boundary to semiconductor technology is blurred, so microsystems and evaluation electronics are increasingly being integrated on a substrate (see smart sensor ).
In practice, two different perspectives are used to look at semiconductor technology:
- The single process view: Here the structure or property changing processes are considered under the aspect of which parameters of the processes lead to the desired physical properties (dimension, conductivity, homogeneity , etc.).
- The integration perspective : in this case, the structure to be implemented - a transistor level or a line level - is considered under the aspect of which individual processes lead to the desired electrical (or more rarely: mechanical or optical) properties of the structure.
Manufacturing processes
The processes used by semiconductor technology are both chemical and physical in nature. In addition to chemical coating processes , etching and cleaning processes, physical methods are also used, such as physical coating and cleaning processes, ion implantation , crystallization or temperature processes ( diffusion , baking , melting, etc.). Other methods use both chemical and physical processes, for example photolithography or chemical-mechanical planarization . In addition, a wide variety of measurement methods are used for characterization and process control.
For the production of (micro) electronic circuits, the processes of semiconductor technology are used in a specific sequence on a substrate. A slice of a semiconductor single crystal (mostly silicon ), a so-called wafer, is usually used as the substrate . Especially in the production of integrated circuits, the function of the electronic components and assemblies is implemented in an area near the surface (max. 1 µm deep, modern CMOS circuits for low voltages below 100 nm deep) on one side of the wafer. In this area, the material properties (especially the electrical ones) of the wafer are specifically changed and, if necessary, structured (material removed and possibly filled with another material). This principle goes back to the planar process invented by Jean Hoerni for the production of transistors . After the definition of the electronic components, these are electrically contacted and connected to one another by applying several structured layers with specific electrical properties (layers with a certain conductivity, insulating layers and conductor tracks ). Electrical components such as capacitors (for example in DRAM ) can be implemented in this area. Further details on this subject can be found in the manufacturing section of the integrated circuit article .
In the following, the methods used in semiconductor technology and their application are grouped according to process sequences for specific functions. Special requirements for all manufacturing processes and production systems result from the dimensions of the components to be manufactured. Depending on the technology node of the microelectronic components, these are less than one micrometer or less (in modern products less than 30 nanometers). That is why the actual manufacturing process, in the manufacturing and wafer handling environment, is required to be free of particles ( clean room manufacturing ).
Preparation of the source material
In a narrower sense, the production of the starting material is not included under semiconductor technology, but should be described here for the sake of completeness: When extracting semiconductor materials ( silicon , germanium , compound semiconductors such as gallium arsenide and silicon germanium ), chemical and chemical-metallurgical processes are used to produce highly pure single - crystal substrates (In a few cases, e.g. for solar cells , polycrystalline substrates are also used). A high-quality substrate material is required to ensure that the components to be implemented later function properly. The aim is to have a pure, homogeneous base material that is crystallized as flawlessly as possible. If these requirements are not met, z. B. randomly increased leakage currents or changed operating points occur in individual transistors . Particular attention is paid to metal contamination. The contamination levels are in the billionths ( ppb range) or trillionths ( ppt range).
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In the case of silicon, a cylinder that is now (2012) up to 300 mm in diameter and more than one meter long is drawn from a melt that has been cleaned several times, starting from a seed crystal (see Czochralski process and zone melting process ). The cylinder is sawn into discs ( wafers ) less than one millimeter thick, which are then ground and polished. In this form, the semiconductor material is usually used in the actual production of the components. In the production facilities in particular, the wafers are then transported in so-called FOUPs ( front opening unified pod , German: uniform holder with frontal opening ); for transport outside of fully automatic manufacturing equipment called FOSBs (engl .: are front opening shipping box , dt. shipping container with frontal opening ) are used.
The German chemical company Wacker / Siltronic is one of the world's largest manufacturers of silicon wafers .
Definition of the structures
In order to be able to realize various components and circuit elements on the substrate, areas must be defined on the starting material that are affected by the following process step and those that are not affected. For this purpose, photolithography - a photographic process - is used (simplified representation):
- On the wafer, a photosensitive is first photoresist spin ( spin coating , Eng .: spin-coating ).
- In a stepper or scanner , the image of a mask is transferred to the light-sensitive photoresist by exposure to strictly monochromatic light (nowadays mostly an expanded laser beam ). Scanners make it possible to expose smaller structures on the wafer than is possible with the stepper. The reason for this is that with the stepper the entire photo mask is displayed as a rectangular image and all uncorrectable errors of the optical lens system have a negative effect. With the scanner, instead of the entire photo mask, only a narrow strip is imaged in the optical lens system. A synchronized movement of the photomask and wafer exposes the entire photomask on the wafer. During this time, exposure parameters such as B. readjusted the focus and so adapted locally to the wafer.
- The photoresist is developed in a chemical bath, which means that the exposed areas (in the case of the so-called positive resist) of the resist are removed, only the unexposed areas remain on the wafer. In the case of negative resist, it is the other way around. The unexposed areas are removed here. A subsequent heat treatment (so-called hard or soft bake) stabilizes the paint structures and solvent residues are expelled.
The parts of the wafer that remain unchanged through the following process steps are thus covered by the photoresist.
- This is followed by a semiconductor process step, such as B. doping , deposition or etching .
- In the subsequent process step, the unexposed photoresist is also removed - this can be done by wet-chemical processes or by incineration in an oxygen plasma .
The structure transfer by means of photolithography - one of the most expensive process steps in semiconductor production - is a challenge in planar semiconductor technology, which is based on increasing the integration density through downsizing. The laws of optics already limit the possibility of further structure reduction (see resolution ). In addition, you now come across other process steps z. B. material-related limits. So allow z. B. the electrical properties of certain standard materials used in the semiconductor process no further structural reduction. The reduction in the cross-section of the conductor tracks also leads to material problems ( diffusion , electromigration, etc.)
The use of new structural materials such as B. the use of special alloys in the conductor track area or the use of modified dielectrics ( low-k and high-k materials), as this means that fundamental changes in technology can initially be avoided. In the long term, however, the transition from planar to 3-dimensional techniques (vertical and horizontal positioning of individual components) appears to be indispensable, since in principle higher component packing densities can be achieved with the same component dimensions. First steps towards 3D technologies are currently being made (see e.g. DRAPA ).
Doping the starting material
In order to change the electrical properties of a semiconductor in certain regions, foreign atoms are introduced locally into the material ( doping ). This is done by ion implantation or diffusion. The foreign atoms are stored at different depths and in different regional concentrations .
- Deep layers with a small vertical extension can be used to place individual transistors in an insulation trough in order to decouple them with respect to their substrate connections.
- Deep layers with a large vertical extent up to the surface of the substrate can be used to create a p-doped well in an n-doped substrate, in which n-channel metal-insulator-semiconductor field effect transistors (n-channel MISFET or . n-channel MOSFET) can be applied.
- Dopings close to the surface can be used as source-drain regions of transistors or as resistance areas.
- Doping in edge areas is one of the methods with which so-called stretched silicon can be realized - areas with an extended lattice structure in which there is increased charge carrier mobility and in which high-performance transistors can therefore be created.
After an implantation, an oven process (tempering) always follows in order to evenly incorporate the implanted foreign atoms, which are located in interstitial spaces, into the crystal lattice and to heal the damage that has occurred in the crystal lattice. (The crystal lattice of the substrate is mechanically damaged by the bombardment with ions)
Deposition and growth of layers
Layers of insulating and conductive materials can be applied to the semiconductor substrate.
- Oxide layers produced in the furnace process by thermal oxidation of the basic material silicon are amorphous and have a low defect density (also at the interfaces), so that they are used as a dielectric for the control electrodes of the field effect transistors, for capacitors and component insulation (see LOCOS and trench insulation ) .
- Oxides or nitrides deposited from the gas phase ( chemical vapor deposition , CVD) are produced, for example, as insulation between different components or as sacrificial layers for etching processes.
- For example, metal layers made of aluminum or copper can be applied by physical vapor deposition or sputtering , from which conductor tracks can then be etched out.
Structuring layers
Etching processes are used to remove areas in the base material or to detach certain areas from deposited layers . A distinction is made between anisotropic (direction-dependent) and isotropic (direction-independent) etching processes.
- The anisotropic plasma etching (dry etching, reactive ion etching, RIE) is the predominant process for structuring today. The material is broken down by accelerating reactive ions onto the wafer surface - so the process has a mechanical / physical and a chemical component.
- The importance of wet chemical etching in the acid bath has declined; today it is mainly used to remove complete layers (sacrificial layers) and to remove process residues.
- To seal the chip surface, i. H. for passivation, a silicate glass is usually deposited. This silicate glass must be removed from the bonding surfaces for external contact. In this case, the glass on the bonding surfaces is removed by means of lithography, and hydrofluoric acid is often used as an etchant. The hydrofluoric acid attacks the silicate glass, while the pure silicon remains intact.
Planarize, clean, measure
Because z. If, for example, conductor tracks produce a certain structural pattern on the surface of the substrate, disturbing unevenness occurs (e.g. disruption of the lithography due to oblique reflection , unevenness in subsequent deposits). The wafer is therefore planarized again at several points in the production process. This can be done by selective etching back or by chemical-mechanical polishing (CMP).
It is not just the polishing that leaves particles on the surface, which must be completely clean and even for the next lithography step. Also z. B. Etching processes leave residues of undesired reaction products. In the first case the wafers are cleaned mechanically by brushing and an ultrasonic bath , in the second case by wet chemical processes and also by ultrasound.
In order to be able to reliably produce the fine structures and thin layers with tolerances of a few nanometers , you need powerful measuring methods for process control. Various spectroscopy and scatterometry methods , atomic force microscopy and various electrical measurement methods as well as particle and defect controls are used.
Semiconductor structures
As a result of the sequence of the individual processes, wells of different conductivity, transistors, resistors, capacitors, conductor tracks and other components are implemented on (or in) the semiconductor substrate. The interaction of the processes on the structure of a transistor type is explained as an example.
Several of the process steps explained above are necessary to produce a transistor level on a semiconductor substrate. The following is a brief summary of the process flows for the production of today's (2009) transistor structures:
- Even before the actual transistor structures are produced, insulation structures are produced between the later transistors; the dominant technique is the grave insulation (engl. shallow trench isolation . See trench technology ). For this purpose, photolithographically corresponding areas between the transistor areas are first masked. This is followed by silicon etching (mostly by reactive ion etching ) and refilling with silicon oxide as well as smoothing of the topography with the help of chemical-mechanical polishing .
- A thin silicon oxide layer is grown on the remaining silicon islands in a furnace - the later gate dielectric of the transistor.
- The material for the gate electrode is deposited on the entire wafer surface - usually a stack of several materials, e.g. B. highly doped silicon, metal and insulation cap.
- The structures of the gate electrodes are defined with a lithography step, then the gate electrode material is etched away wherever there was no photoresist left after development.
- In a furnace process, an oxide is formed on the now open flanks of the gate structures for insulation and as a spacer for the subsequent processes.
- First the n-channel MOSFET transistor areas, then the p-channel transistor areas, are covered by means of lithography in order to dop the source-drain areas with the correct foreign atoms ( ion implantation ).
- To close off the transistor level from the following wiring levels, a thick layer of insulation is applied to the entire wafer. Wherever the gate structures are, bumps form in the insulation layer, which have to be removed by chemical-mechanical polishing.
The production process for transistors that is common today also includes other processes, e.g. B. various auxiliary dopings or thicker gate dielectrics for thick oxide transistors.
Status and outlook
In less than a decade, semiconductor technology has become a key technology of the 20th century. The Cold War and the resulting military and information technology needs were obstetricians, catalysts and are still the mainspring of development today (see e.g. the latest developments in processor technology , data storage , signal processing , optoelectronics, etc.). The construction of a stable production-technological framework was achieved through the commercial manufacture of microelectronic circuits on a large industrial scale, e.g. B. for the first calculator achieved.
The role of the technological pioneer that semiconductor technology has played for decades is slowly beginning to fade. Other technologies like biotechnology have started to take over the baton. Semiconductor technology is currently in the transition from a young technology to a mature and consolidating technology ( technology life cycle ). In the future, the scene will primarily be determined by small, from a purely technical point of view, quite challenging innovation steps and evolutionary detail improvements. The aim is and will be to exhaust the possibilities of the existing techniques. Larger leaps in development, hardly to be expected in large-scale production techniques anyway, are less likely with semiconductor technologies. This is true at least for the industries that are dedicated to the manufacture of integrated circuits. Other sub-areas of microelectronics such as screens or solar cells still have great research potential.
The research and technology development for the production of integrated circuits therefore takes place along so-called roadmaps (German: »project plan«). The relevant roadmap is the ITRS ( International Technology Roadmap for Semiconductors ), which has existed since 1988 ; the companies involved make up more than 90% of global semiconductor production. In the ITRS, the long-term development goals of the semiconductor industry are planned 15 years in advance and regularly adapted to current developments. The development stages or focal points ( nodes ) are defined using the term structure size (or the minimum structure size ). The directional guidelines for development are intended to identify technological bottlenecks at an early stage and set research incentives. As a result, the industry has succeeded in upholding Moore's law . Since production now operates in areas that were considered physically “impossible” 20 years ago, it is to be expected that the end of this development will be postponed for a further few years. The end is reached at the latest with the manufacture of components with structure sizes (<10 nm) of a few atoms based on today's silicon-oriented technology. New developments with novel modes of operation are necessary here in order to follow the trend of Moore's law. In the chapter “Emerging Research Devices ” (ERD) the ITRS deals with potential technologies that are based on the existing technology. In addition to technologically related concepts such as FeRAM or layered dielectrics ( e.g. engineered tunnel barrier memory ), this also includes concepts that will probably not be ready for use in the next ten years, such as memories and circuits based on conductive macromolecules or single-electron transistors .
Like other cutting-edge technologies, semiconductor technology also causes increasing costs in order to keep existing technology evolving, especially in the area of circuit manufacture. The empirical development work is necessary in many areas, since corresponding simulations do not yet reproduce the processes with the required accuracy. This is due on the one hand to the high tolerance requirements as well as the lack of physical explanations for the processes in the nanometer range, for example chemical-mechanical polishing or the exact sequence of the coating process during atomic layer deposition . As in other technical disciplines , work on the simulation of process sequences is also increasing in semiconductor technology. In addition to the simulations used for decades in the development and verification of circuits, more and more complete production processes for semiconductor components are being simulated.
In photovoltaics, in addition to the development costs, there are also the comparatively high module prices for the end customer. For a long time, a high need for subsidies was necessary here in order to be able to carry out cost-covering research and at the same time to offer attractive product prices in order to position the technology against conventional power plants (coal, gas, etc.). The aim of this policy, especially in Germany, was then as now to promote alternative and regenerative energy concepts.
environmental Protection
At the beginning of the mass production of semiconductor components, very little attention was paid to environmental aspects. In Silicon Valley in particular , large-scale groundwater pollution occurred in the late 1960s and early 1970s. For the first time, these incidents revealed the downside of an industry that was previously considered to be particularly progressive.
Indeed, environmentally hazardous substances are produced, used and emitted in connection with the manufacture of microelectronic components. These include u. a. numerous heavy and semi-metals, substances that destroy the ozone layer and greenhouse gases. Residues occur - possibly in converted and mixed form - as solids, liquids and gases. Many of the starting materials are not recycled for technical or economic reasons.
Since the mid-1980s, legal regulations have come into force in many industrialized countries, which have prompted industry to implement measures to locally reduce the potential for environmental hazard. In the booming regions of Asia, however, environmental protection aspects are often subordinated to economic interests. Voluntary regulations such as the international standardization that began in the mid-1990s, e.g. B. ISO 14001 ( Environmental Management Systems ) naturally have little effect there as long as they are not supported by national law.
literature
- Ulrich Hilleringmann: Silicon semiconductor technology: Basics of microelectronic integration technology . 5th edition. Vieweg + Teubner, 2008, ISBN 3-8351-0245-1 .
- Dietrich Widmann, Hermann Mader, Hans Friedrich: Technology of highly integrated circuits . 2nd Edition. Springer, Berlin 1996, ISBN 3-540-59357-8 .
Web links
- www.halbleiter.org - basics of semiconductor technology