Planar technology
The planar (also planar process ) is in the semiconductor manufacturing employed process for the production of transistors ( planar transistors ), and integrated circuits . The process was developed (1958) and patented by Jean Hoerni at Fairchild Semiconductor for the production of lateral bipolar transistors . With planar technology and its further development, it was possible for the first time to place and connect several transistors, diodes and resistors on a substrate (chip).
Background and functionality
The essential point of planar technology is the change in the partial process sequence compared to the usual production of mesa components (see mesa transistor ). In the case of mesa components, the passivating oxide layer was only deposited after the base had been manufactured. It was mainly used to mask the emitter diffusion zone and was later removed - at that time it was assumed that the oxide was contaminated during diffusion and had to be removed. The mesa structure therefore had two major disadvantages: on the one hand, it required large etched areas (area-intensive) in order to make the transistors sufficiently small for "high-frequency applications"; Surfaces or the failure of the transistor caused.
Hoerni's idea was to embed the sensitive transition areas of the differently doped zones (cf. pn junction ) in the substrate material and to passivate the surface with a non-conductive layer applied before diffusion, cf. thermal oxidation of silicon . In this way, the sensitive areas could be protected from contamination during production.
Hoerni achieved the production of the active areas (base, emitter and collector, later with the MOSFET source and drain) by locally opening the passivation layer through photolithographic structuring and etching of the passivation layer, thus releasing the semiconductor crystal locally. The exposed areas could then be doped by diffusion or contacted by the connecting wires. The planar surface compared to the production sequences used at that time also simplified the repeated use of a photolithographic structuring. Together with the renewed application of a passivating layer to the areas already exposed, this made possible further doping of partial areas or other areas and the production of electrical contacts.
Modified planar process for the production of a MOS field effect transistor
The MOS field effect transistors used nowadays in integrated circuits can also be manufactured using planar technology. There are very different process sequences for the production of the gate electrode and the source and drain regions. The basic concept shown below is essentially also used in the manufacture of today's top microelectronics products. However, due to the more complex structure of the transistors used there, further structuring, deposition and etching steps are required.
After the passivation, there is a further photolithographic structuring and local opening of the passivation layer for contacting the active regions and the gate electrode. The connection of several transistors to a circuit is made by subsequently deposited and structured conductor track levels .