LOCOS process

LOCOS , short for English local oxidation of silicon (dt. "Local oxidation of silicon ") is, in the semiconductor technology, a method for electrical isolation of semiconductor devices such as transistors . For this purpose, the silicon wafer is masked at selected points, that is, provided with a structured protective layer, and the exposed silicon is then locally oxidized close to the surface at high temperatures in an oxygen-rich atmosphere , cf. thermal oxidation of silicon . In this way, an electrical insulation area made of silicon dioxide is created on the substrate surface between the electrically active silicon areas for the components .

For a long time, the LOCOS process was the preferred method in semiconductor technology for the production of the aforementioned isolation areas. However, since the process is relatively space-intensive and has further disadvantages (see below), it was replaced by so-called trench insulation in the mid-1990s in the industrial production of highly integrated circuits, i.e. with structure sizes of 0.25 µm and smaller .

background

Isolation of components

One of the main driving forces of microelectronics is a steadily increasing integration density of the active components on a substrate, that is, both the components and the spaces in between are getting smaller from generation to generation. In addition to production-related problems, this increasing reduction in size also leads to electrical problems such as crosstalk of signals on conductor tracks or increasing leakage currents due to the smaller insulation distance. In the history of development, this problem has led to various insulation techniques and their use in integrated circuits , including LOCOS technology.

Before the development of planar technology , transistors and diodes were usually manufactured as mesa components (see mesa transistor ). Despite the relatively far apart and virtually free-standing components, the reduction of the relatively large surface leakage currents, for example caused by interfacial charges, was one of the important challenges. As early as 1959, a working group led by Martin M. Atalla presented a technology in which these leakage currents could be drastically reduced by means of silicon dioxide that had grown thermally directly on a silicon substrate . This formed the basis of the process known today as the LOCOS process, which was developed from 1966 by E. Kooi at the Philips Natuurkundig Laboratorium .

The Planar and Planox Process

The discovery of (electrical) surface passivation a few years later led to the industrial use of this technology. A full-area field oxide was applied to the silicon substrate (silicon wafer ) that has now been used as standard (thermal oxidation). In order to manufacture the desired transistor and diode elements , the silicon dioxide was then wet-chemically etched (structured) at the appropriate points so that the silicon substrate is accessible for the diffusion or implantation processes. However, this approach has several major disadvantages. For example, photoresist , which is used in photolithographic structuring for subsequent process steps, can accumulate at the steps that occur during the structuring of the oxide (at that time in the range of 1.5 µm) and thus reduce the resolution . Since the wet chemical silicon dioxide etching is an isotropic etching process (the etching is the same in all spatial directions), resist mask adjustments are necessary to compensate for the undercuts. Another problem is the limited conformance of the metallization at the step edges. As a result, conductor track constrictions occur and the associated local increase in current density leads to damage and premature aging due to electromigration - the conductor track material aluminum , which was used until the turn of the millennium, is relatively "susceptible" to electromigration. In order to further increase the packing density of the microelectronic circuits, i.e. to accommodate as many components as possible in the smallest possible area, it was necessary to achieve the smoothest possible topography , i.e. to avoid or reduce the steps and unevenness.

The “Planox” process presented by F. Morandi in 1969 showed an initial improvement. The fact that a silicon nitride layer protects the silicon substrate underneath from oxidation has already been exploited . In the Planox process, therefore, a silicon nitride layer was first deposited over the entire surface of the silicon wafer, then photolithographically structured and the nitride etched. This was followed by oxidation of the wafer in an oven until the oxide in the unmasked areas has grown somewhat above the level of the nitride layer. Now the nitride was selectively etched with hot phosphoric acid in order to expose the areas in which the active areas of the transistors will later be located. In a second oxidation step, this area was brought to the level of the isolation areas, this is possible because the oxide layer grows significantly faster with thinner layer thicknesses. With this process, components could be produced in which the approximately 2 µm thick oxide was largely in the silicon substrate and the highest level was only around 0.5 µm.

Nevertheless, it was not until 1970 by Appels et al. The technology of local oxidation of silicon (LOCOS) presented the breakthrough. The LOCOS technology is very similar to the Planox process and remedies these limitations of the planar process by making the transitions between the layers less abrupt.

Procedure

With the LOCOS technology, a process opposite to the Planox technology is used. The areas in which the later insulation oxide should be located are exposed. A silicon nitride layer (Si ₃ N ₄ layer), which is structured using the usual etching techniques, serves as a mask for the structured oxidation process. Compared to silicon, the oxidation of silicon nitride is several orders of magnitude slower, so that there is virtually no influence from the oxidation process. The high temperature stress caused by the oxidation process leads to tension between the silicon substrate and the silicon nitride mask, which is why an intermediate layer of silicon oxide (called pad oxide) is necessary to alleviate the tension and thus prevent the nitride layer from flaking.

Process steps of the LOCOS technology

A typical LOCOS process consists of the following steps:

1. Preparation of the silicon substrates: This usually includes the removal of particles and organic contaminants, which can be done, for example, by means of RCA cleaning .
2. Deposition of a 10–20 nm thin silicon dioxide layer: It serves as a buffer against mechanical tension. These occur between the silicon substrate and the silicon nitride layer (mask, see 3.) due to the higher thermal expansion coefficient and the high temperature stress caused by the thermal oxidation process. Among other things, this would lead to crystal defects. The oxide layer is therefore called pad or buffer oxide and is deposited from the gas phase using a CVD process, often a TEOS oxide.
3. Deposition of a 100–200 nm thick silicon nitride layer, which is hardly influenced chemically by the oxidation process and which protects the masked areas from oxidation. It is generally manufactured using an LPCVD process.
4. Photolithographic structuring and etching of the nitride and oxide layer so that the silicon substrate is accessible for the oxidation process
5. Thermal growth of SiO ₂ on silicon in the unmasked areas. In a narrow sense, thermal oxidation is not a coating, but rather a layer modification. Oxygen reacts with the pure silicon substrate to form silicon dioxide. Two effects are essential: firstly, silicon is “consumed” so that the resulting oxide layer grows partly in the area of ​​the substrate, and secondly, the strong storage of oxygen and crystal modification leads to volume growth, so that around 55 percent of the desired oxide layer thickness lies in the previous silicon substrate. Another effect is the lateral diffusion of oxygen under the nitride-masked areas (see bird's beak ).
6. Removal of the nitride mask by wet chemical etching with phosphoric acid at 150–175 ° C. Then short etching the pad oxide with buffered HF solution (Engl. Buffered oxide etch , BOE). The oxide etching continues to level the transition and reduce the size of the bird's beak.

Advantages and disadvantages

Compared to the previously used Planox technology, the LOCOS technology has several decisive advantages. With LOCOS, the sharp edges and steps in the topography of the surface are significantly reduced. This allows an improved photoresist application in subsequent processes and a better conformity of the metallic conductor tracks , that is, significantly less constrictions of the conductor tracks and thus a lower risk of connection problems, no local increases in resistance and a low susceptibility to electromigration . In this way, the minimum structure sizes that could be produced could be reduced to around 1 µm compared to the planar technology that was conventional at the time.

As the oxide grows in depth during the thermal oxidation, the insulating oxide barrier protrudes clearly into the substrate, which hinders the crosstalk of the neighboring transistors, i.e. the electrical insulation of the active components on the substrate is improved.

Disadvantages of the LOCOS process are the still non-planar topography after oxidation, the formation of a transition area from the oxidized to the non-oxidized area, the so-called bird's beak , and the deposition of a silicon nitride layer at the interface with the silicon substrate, the white ribbon effect. Above all, the resulting bird's beak limits the practically achievable integration density of the components and the non-planar topography makes the subsequent photolithography steps more difficult, as it hinders the even application of photoresist and locally changes the focus required for exposure. For these reasons, among others, numerous further developments of the original LOCOS process have been developed in the industry, which reduce the parasitic effects and enable greater integration of the circuits, see section Further developments . However, some of these techniques are significantly more complex and thus more costly, and they can only mitigate the disadvantages and not completely remove them. Therefore, an alternative technique that continued in the 1990s by, grave insulation (Engl. Shallow trench isolation , STI, or English. Box isolation technique ). Deep-etched trenches in the silicon are filled with silicon oxide ( TEOS - CVD ). This is not possible with the thermal oxide of the LOCOS technology, since the change in volume during the oxide growth creates excessive mechanical stresses in the trench and leads to defects. Compared to LOCOS technology, trench insulation allows significantly better lateral insulation (also in deeper regions) and can also be produced in an even more space-saving manner, which in turn enables a higher packing density.

Bird's beak

Bird's beak after a normal LOCOS process

As already mentioned in the short process summary, the silicon dioxide grows under the edge of the actually masked areas during thermal oxidation. The reason for this is the isotropic and thus lateral oxygen diffusion both in the LOCOS oxide and in the pad oxide. The result is an oxide structure that is characteristic of the LOCOS process, the edge of which runs down to a micrometer below the nitride layer and is called a bird's beak due to its profile .

As the oxidation proceeds, the growth of the oxide layer at the edges of the masked areas causes the nitride mask to bend (away from the substrate). Since the mechanical stresses during the process with direct contact between silicon and silicon nitride would be too great due to the different lattice spacing - the nitride layer would flake off due to the bending - the pad oxide is necessary as a buffer.

White ribbon or kooi effect

Reaction paths in the white ribbon effect during a normal LOCOS process

The white ribbon or Kooi effect, named after E. Kooi, a co-developer of the LOCOS technology, is a parasitic effect in the LOCOS process. He describes the formation of a thin silicon nitride layer between the pad oxide and the silicon substrate in the outflow area of ​​the bird's beak. This is evident in examinations by means of bright field microscopy as a whitish ribbon . This undesired layer formation occurs mainly in the case of a so-called wet oxidation layer . This method is used by default for thicker oxide layers, as it shows faster layer growth compared to dry oxidation in an oxygen-rich atmosphere without water vapor. Given the long process times for thick oxide layers, this offers economic advantages in particular.

The wet oxidation is carried out in an atmosphere enriched with water vapor at temperatures above 1100 ° C. Here the diffusion of hydroxide ions (OH ^- ) through the silicon nitride layer leads to a slight oxidation of the silicon nitride layer on the pad oxide side. Among other things, ammonia is formed as a reaction product of this oxidation . The ammonia in turn diffuses through the pad oxide to the silicon substrate. The high temperatures cause thermal nitridation of the silicon, i.e. ammonia reacts with the silicon to form silicon nitride, and the silicon nitride layer observed by Kooi forms between the pad oxide and the silicon substrate.

${\displaystyle \mathrm {Si_{3}N_{4}+6\ OH^{-}\rightarrow 3\ SiO_{2}+2\ NH_{3}+N_{2}} }$

${\displaystyle \mathrm {3\ Si+4\ NH_{3}\rightarrow Si_{3}N_{4}+6\ H_{2}} }$

The effect only occurs in the area of ​​the bird's beak, because here the rate of oxidation of silicon is low and the diffusion path for ammonia is short. With regard to the overall circuit production process, this nitride accumulation must be removed before the subsequent oxidation step for the so-called gate oxide, which is used as a dielectric in the MISFET , as it hinders or prevents oxide growth.

Further developments

Comparison of different LOCOS processes in the transition area

The bird's beak and white ribbon effect as well as the no longer flat topography after oxidation are the main disadvantages of the standard LOCOS technology. For this reason, the further developments were pushed forward quickly and numerous variants were developed in order to reduce one or more of these disadvantages through a modified process sequence. The most important further developments are:

1. semi recessed LOCOS and fully recessed LOCOS
2. SPOT ( self-aligned planar oxidation technology , also super planar oxidation technology )
3. SILO ( sealed interface local oxidation )
4. Polysilicon Buffered LOCOS
5. SWAMI ( side wall mask isolatated )
6. FUROX ( FUlly Recessed Oxide )

Fully-recessed LOCOS

Schematic representation of the fully recessed LOCOS process

The fully recessed LOCOS process ( fully recessed) is a comparatively simple way of leveling the surface topography further and introducing the field oxide deeper into the substrate. For this purpose, after the structuring (1) of the pad oxide-nitride layer stack, the silicon substrate is anisotropically etched back (2). This creates trenches in the silicon, the depth of which is approximately 50% later field oxide thickness. There are different variants for etching, for example it can be wet-chemically isotropic with a nitric acid - hydrofluoric acid solution, wet- chemically anisotropic with a potassium hydroxide solution or by dry etching . This is followed by the thermal oxidation step (3), with the oxide growing 45% into the silicon substrate and 55% upwards. It fills the etched trench. After the oxidation, the silicon nitride mask is removed (4) and a relatively flat surface is created.

The main advantage of the fully recessed LOCOS process is the good electrical insulation properties, e.g. B. a low leakage current in the off-state in field effect transistors. They result primarily from the greater insulation length, i.e. the length of the Si-SiO ₂ interface from one active area to the next. The disadvantage is a slightly increased length of the bird's beak and the formation of " bird's head " on the side areas. The latter represents an elevated topography and can in turn lead to complications of both step overlapping during the metallization.

SPOT technology

The SPOT technology is a way of obtaining a very flat topography after oxidation based on the standard LOCOS process. The LOCOS process is essentially carried out twice for this purpose.

First, after the field oxidation, the field oxide is completely removed again by wet chemical etching. By choosing a suitable etcher with high etching selectivity between silicon oxide and silicon nitride, the masking nitride remains virtually unchanged. After the etching, there is a full-surface nitride deposition that conforms to the edges, that is, the nitride layer has the same thickness everywhere, even in the areas of the underside of the mask nitride that was pushed up by the bird's beak, which is exposed after the etching. Before the oxidation, however, this second nitride layer must be removed again over a large area. Only at the edges of the bird's beak produced during the first oxidation is it intended to limit the diffusion under the mask nitride, so that the bird's beak cannot spread further under the mask nitride during the subsequent oxidation. This anisotropic etching step is carried out by reactive ion etching of the nitride. Another oxidation step now follows, consisting of a brief pad oxidation and a wet thermal oxidation for the field oxide. After the required layer thickness has been achieved, the nitride layers can now be removed according to the standard process.

The end result is an almost flat wafer surface, which however still has a transition area (part of the bird's beak) between the active area and the oxidation trough. Parasitic effects (white ribbon effect, etc.) also continue to occur. The additional process steps also make the process much more time-consuming and costly.

SILO technology

The SILO technology (SILO = sealed interface local oxidation , dt. "Local oxidation with sealed interface") was specifically developed to suppress the bird's beak and the white ribbon effect.

In contrast to the conventional LOCOS process, with the SILO-LOCOS process the surface is first coated with a 4–10 nm thin layer of thermal silicon nitride (Si ₃ N ₄ ). The thermal nitriding is comparable to the thermal oxidation of silicon . It takes place, for example, under an ammonia atmosphere (NH ₃ ) at around 1200 ° C. Silicon reacts with ammonia to form silicon nitride and hydrogen (H ₂ )

${\displaystyle \mathrm {3\,Si+4\,NH_{3}\rightarrow Si_{3}N_{4}+6\,H_{2}} }$

The stresses in the nitride layer, which are critical in the conventional LOCOS process, must be tolerated due to the small thickness and do not negatively influence the subsequent processes. In the second step, the nitride is coated with a pad oxide and a thick CVD nitride layer. Then the entire stack of layers is structured with a photoresist mask and reactive ion etching.

The thermal nitride layer is intended to protect the silicon surface from oxygen diffusion under the structure edges during field oxidation. The relatively complex structure of the masking layer is necessary because the thin nitride layer would oxidize completely during the field oxidation and therefore cannot be used as a mask on its own. The production effort is increased by an additional two process steps due to the additionally required CVD oxide deposition.

The properties achieved by the SILO technology are good, because both the formation of the bird's beak (reduction by up to 65%) and the white ribbon effect can be effectively suppressed by sealing with the thermal nitride layer. With regard to the topography after oxidation, the SILO technology does not have any advantages over the conventional LOCOS process, i.e. a step of around 55% of the field oxide thickness is also created.

In order to reduce the stress caused by thermal nitriding, it can alternatively be replaced by an LPCVD nitride. This is possible because a natural oxide is inevitably located between the silicon surface and the nitride as pad oxide and serves as an adhesion promoter.

Polysilicon-buffered LOCOS technology

The expression of the bird's beak can be achieved with the conventional LOCOS technology by reducing the layer thickness of the pad oxide or increasing the layer thickness of the mask nitride. However, this causes additional mechanical stress during the oxidation and harbors the risk that, for example, the nitride layer can become detached. The polysilicon-buffered LOCOS technology ( poly-buffered LOCOS , PBL) is a further development that specifically addresses this point and primarily aims to reduce the bird's beak and the white ribbon effect.

An additional 20-50 nm thick layer of polysilicon is inserted between the buffer oxide and the nitride layer; it serves partly as a sacrificial layer and is completely removed again after the process. The additional layer reduces the mechanical stress in the nitride mask on the one hand and the expansion of the bird's beak on the other. During the oxidation, the polysilicon layer absorbs oxygen more than the silicon substrate (shorter diffusion path, higher diffusion speed). As a result, less oxygen is available in this area for the oxidation of the substrate material. The result is that less substrate is used. Due to the lower mechanical stress in the nitride layer, thinner pad oxide and thicker nitride layers can be used, which also help to reduce the bird's beak and have a positive effect on the structural integrity.

The additional process steps for the production and removal of the non-oxidized polysilicon layer are negative for the use of the polysilicon-buffered LOCOS technology. The polysilicon is typically removed by plasma etching. Depending on the grain size of the layer, increased surface roughness can arise, which leads to problems in the later gate areas. The use of amorphous silicon can significantly reduce surface roughening . However, at the high temperatures used in the thermal oxidation of silicon, recrystallization of the amorphous layer can occur. One way of preventing this is to dop the layer with nitrogen.

SWAMI-LOCOS technology

The SWAMI LOCOS technique (SWAMI of English sidewall-masked isolation , dt. Sidewall masked isolation ) was introduced in 1982 by Chiu and others. This is also a LOCOS variant in which the silicon is first etched back ( recessed ) and the trench is then filled up again by volume expansion caused by oxidation.

As with the fully recessed LOCOS process, a layer stack consisting of a pad oxide and a silicon nitride layer is deposited over the entire surface of the wafer. The active areas are then photolithographically masked and the layer stacks are removed in the areas of the later field oxide by reactive ion etching (RIE). In a further step, the silicon substrate is anisotropically etched, either also by RIE or wet-chemically with a KOH solution. The depth of the etch is approximately 55% of the desired thickness of the subsequent field oxide.

Now the SWAMI-specific process steps follow. First, the exposed silicon areas (trenches) are briefly thermally reoxidized. On the one hand, this serves to “round off” the angular silicon trench structure, and on the other hand, the thin oxide (hereinafter referred to as oxide-II) serves as a buffer layer to reduce mechanical stress between the silicon and the nitride layer. Then a second stack of layers made up of an Si ₃ N ₄ and an SiO ₂ layer (nitride-II and oxide-III) is deposited over the entire surface. Among other things, good side coverage of the etched structures is important, which is why a chemical vapor deposition (CVD) process is usually used. In the next step, the oxide III layer is etched using a highly anisotropic process. The oxide layer on the sidewalls is not thinned because of the anisotropic nature of the etching and remains as a spacer (engl. Spacer ) was obtained. After the spacer (oxide-III) has been removed, a silicon mesa remains, the side walls of which are protected by the nitride-II and the oxide-II. The length of the protruding nitride on the trench bottom of the recessed silicon is chosen so that the growth of the bird's beak into the later active areas is minimal. The boundary of the active areas is determined by the edge of the first nitride. During the subsequent thermal oxidation, this area is filled up again by the field oxide until the oxide has reached the level of the original silicon surface. The thin sidewall nitride is bent upwards.

After removing the masking and buffer layers, an almost planar surface is obtained. The expression of the bird's beak or the bird's head is effectively suppressed. The most important advantages of the SWAMI-LOCOS technology are therefore an increase in the packing density and hardly any restrictions with regard to the field oxide thickness. The white ribbon effect does not occur either.

literature

• Ulrich Hilleringmann: Silicon semiconductor technology: Basics of microelectronic integration technology . 5th edition. Vieweg + Teubner, 2008, ISBN 978-3-8351-0245-3 .
• Stanley Wolf, Richard N. Tauber: Silicon Processing for the VLSI Era, Vol. 2: Process Integration . 5th edition. Lattice Press, 1990, ISBN 0-9616721-4-5 , pp. 20-45 .

Web links

• Helmut Föll: LOCOS Process. Basic Concept of Local Oxidation. In: Electronic Materials. Retrieved December 2, 2008 . 

Individual evidence

1. ↑ MM Atalla, E. Tannenbaum, EJ Scheibner: Stabilization of silicon surfaces by thermally grown oxide . In: Bell System Technical Journal . tape 38 , 1959, pp. 749 .
2. ↑ The invention of Locos , Else Kooi, 9 jan. 1991, IEEE, ISBN 0780303024 .
3. ^ E. Kooi, The history of LOCOS The history of LOCOS, Semiconductor Silicon, 1998, HR Huff, U. Gösele en H. Tsuya, p. 1638.
4. ^ Ingolf Ruge, Hermann Mader: Semiconductor technology . Springer, 1991, ISBN 3-540-53873-9 , pp. 226-227 .
5. ^ F. Morandi: The MOS planox process . In: Electron Devices Meeting, 1969 International . tape 15 , 1969, p. 126 , doi : 10.1109 / IEDM.1969.188179 .
6. ↑ F. Morandi: Planox process Smooths path to greater density MOS . Electronics, 1971, p. 44-48 .
7. ^ J. Appels, E. Kooi, MM Paffen, JJH Schatorje, WHCG Verkuylen: Local oxidation of silicon and its application in semiconductor-device technology . In: Philips Research Reports . tape 25 , no. 2 , 1970, p. 118-132 .
8. ↑ Chue San Yoo: Semiconductor Manufacturing Technology . World Scientific, 2008, ISBN 978-981-256-823-6 , pp. 84 ff .
9. ↑ Ulrich Hilleringmann: Silicon semiconductor technology: Basics of microelectronic integration technology . 5th edition. Vieweg + Teubner, 2008, ISBN 978-3-8351-0245-3 .
10. ^ Stanley Wolf, Richard N. Tauber: Silicon Processing for the VLSI Era, Vol. 2: Process Integration . 5th edition. Lattice Press, 1990, ISBN 0-9616721-4-5 , pp. 20-45 .
11. ^ KY Chiu, JL Moll, KM Cham, Jung Lin, C. Lage, S. Angelos, RL Tillman: The sloped-wall SWAMI — A defect-free zero bird's-beak local oxidation process for scaled VLSI technology . In: IEEE Transactions on Electron Devices . tape 30 , no. 11 , 1983, pp. 1506-1511 , doi : 10.1109 / T-ED.1983.21329 .
12. ↑ H.-H. Tsai, S.-M. Chen, H.-B. Chen, C.-Y. Wu: An evaluation of FUROX isolation technology for VLSI / nMOSFET fabrication . In: IEEE Transactions on Electron Devices . tape 35 , no. 3 , 1988, pp. 275-284 , doi : 10.1109 / 16.2451 .
13. ^ Stanley Wolf, Richard N. Tauber: Silicon Processing for the VLSI Era, Vol. 2: Process Integration . 5th edition. Lattice Press, 1990, ISBN 0-9616721-4-5 , pp. 28-31 .
14. ↑ Kazuhito Sakuma, Yoshinobu Arita, Masanobu Doken: A New Self-Aligned Planar Oxidation Technology . In: Journal of The Electrochemical Society . tape 134 , no. 6 , 1987, pp. 1503-1507 , doi : 10.1149 / 1.2100700 .
15. ↑ J. Hui, TY Chiu, S. Wong, WG Oldham: Selective oxidation technologies for high density MOS . In: Electron Device Letters, IEEE . tape 2 , no. 10 , 1981, pp. 244-247 , doi : 10.1109 / EDL.1981.25419 .
16. ↑ YP Han, B. Ma: Isolation process using polysilicon buffer layer for scaled MOS / VLSI . In: The Electrochem. Society Extended Abstracts . No. 1 . Electrochemical Society, 1984, pp. 98 .
17. ↑ YP Han, B. Ma: Isolation process using polysilicon buffer layer for scaled MOS / VLSI . In: VLSI Science and Technology / 1984: Materials for High Speed ​​/ high Density Applications: Proceedings of the Second International Symposium on Very Large Scale Integration Science and Technology . Electrochemical Society, 1984, pp. 334 .
18. ↑ T. Kobayashi, S. Nakayama, M. Miyake, Y. Okazaki, H. Inokawa: Nitrogen in-situ doped poly buffer LOCOS: simple and scalable isolation technology for deep-submicron silicon devices . In: IEEE Transactions on Electron Devices . tape 43 , no. 2 , 1996, p. 311-317 , doi : 10.1109 / 16.481733 .
19. ↑ KY Chiu, JL Moll, J. Manoliu: A bird's beak free local oxidation technology feasible for VLSI circuits fabrication . In: IEEE Transactions on Electron Devices . ED-29, No. 4 , 2002, p. 536-540 , doi : 10.1109 / T-ED.1982.20739 .
20. ↑ KY Chiu, JL Moll, J. Manoliu: A bird's beak free local oxidation technology feasible for VLSI circuits fabrication . In: IEEE Journal of Solid-State Circuits . tape 17 , no. 2 , 1982, p. 166-170 , doi : 10.1109 / JSSC.1982.1051711 .
21. ↑ KY Chiu, JL Moll, KM Cham, J. Lin, C. Lage, S. Angelos, RL Tillman: The sloped-wall SWAMI- A defect-free zero bird's-beak local oxidation process for scaled VLSI technology . In: IEEE Transactions on Electron Devices . ED-30, No. 11 , 1983, pp. 1506-1511 , doi : 10.1109 / T-ED.1983.21329 .