Trench isolation

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The trench isolation ( English shallow trench isolation , STI, also box isolation technique , BIT) is a method of the semiconductor technology for the electrical isolation of individual components (mostly MIS field effect transistors ) on integrated circuits (IC). For this purpose, trenches about 250 to 700 nm deep are created between the electrically active areas and filled with an electrically insulating material (usually silicon dioxide). A similar process is used in other semiconductor products, such as high-power bipolar transistors or analog integrated circuits. Trench depths of approx. 5 µm are used for this. To distinguish it from the "flat grave isolation" (STI, shallow = dt. Flat ), this process is (engl. As "deep grave Isolation" deep trench isolation , DTI, deep = dt. Deep ), respectively.

In addition, there are a number of different insulation methods that also use a more or less deep trench filled with electrically insulating material.

background

For years, the STI technology has been the preferred insulation technology (for the electrical insulation of individual components) in CMOS circuits (especially for technology nodes below 0.25 µm). The process was developed as previously used techniques (especially LOCOS process and extensions) is no longer sufficient to at the used minimum feature size (engl. Feature size ) to ensure sufficient insulation. The LOCOS technology had some major disadvantages, for example the formation of “bird's beaks” limits the packing density and the insulation effect is rather superficial. In addition, the LOCOS technology has a negative effect on the topography of the chip surface, so that subsequent steps are hindered as a result of the lithographic structuring that is difficult to carry out. The main disadvantage of the STI process compared to LOCOS is the higher number of process steps.

STI process

The STI manufacturing process as a technology cut

The STI process is usually one of the first manufacturing steps in the manufacture of integrated circuits. The starting material is an unstructured silicon wafer. The layer thicknesses specified in the following basic description are orientation values ​​and can in some cases differ significantly in actual processes.

The first process stage (Fig. 1) includes the deposition of the layer stack, which will be structured later. For this purpose, a very thin silicon dioxide layer (approx. 20–40 nm) is first created by thermal oxidation of silicon . This oxide serves as a buffer layer for the subsequent silicon nitride layer, which is intended to reduce the mechanical stresses that arise due to lattice constants of different sizes and thermal expansion coefficients and thus improve the adhesion of the nitride layer. The oxide is then via chemical vapor deposition at low pressure (engl. Low pressure CVD , LPCVD ) with a silicon nitride layer (approximately 100-150 nm) coated; the nitride layer later serves as a stop layer for the CMP process ( chemical-mechanical planarization ). Finally, a photoresist is applied by spin coating .

The second process stage that follows (Fig. 2) is the uncovering of the later insulation trays. For this purpose, the previously applied photoresist is structured photolithographically and the later trench areas are thus masked. This is followed by the anisotropic etching of the layer stack and the trench regions (approx. 250-700 nm deep), for example by reactive ion deep etching (DRIE). In order to remove polymer residues from the RIE step, a short wet chemical etching step with hydrogen fluoride solution ( hydrofluoric acid ) follows , which at the same time slightly undercuts the buffer oxide (Fig. 3).

Now the trenches are filled with the insulating material silicon dioxide. The deposition takes place over the entire area using a CVD process until the trenches are overfilled. The CVD process must have the property of filling even smaller structures with higher aspect ratios homogeneously. This is possible, for example, with HDP-TEOS-PECVD (High Density Plasma Tetraethylorthosilicate - Plasma Enhanced CVD ). In order to obtain a qualitatively higher-quality interface between the silicon and the CVD silicon dioxide, i.e. an interface with few interface charges, a thermal silicon dioxide, the so-called liner oxide , is often produced on the trench surfaces before the CVD coating (Fig. 4, approx. 20-50 nm). This also reduces damage caused by the etching process and mechanical stress on the trench edges.

After the trenches have been filled, the wafer is completely covered with a layer system made of silicon dioxide and silicon nitride. For the subsequent manufacturing steps, such as building the transistor structures, it is therefore necessary to expose the silicon substrate again. This is also done with regard to the improvement of the surface of the wafer ( topography ) - especially important for photolithography - by removing the layers above the wafer by chemical-mechanical polishing (CMP) of the silicon dioxide, the so-called oxide CMP . The silicon nitride serves as a stop layer for the polishing process. This is followed by the wet-chemical removal of the silicon nitride stop layer (with phosphoric acid ) and etching back of the remaining oxide with hydrofluoric acid until the buffer oxide layer is removed.

literature

  • Gary S. May, Simon M. Sze : Fundamentals of Semiconductor Fabrication . Wiley & Sons, 2003, ISBN 0-471-23279-3 .
  • Stephen A. Campbell: The Science and Engineering of Microelectronic Fabrication . 2nd Edition. Oxford University Press, 2001, ISBN 0-19-513605-5 .

Individual evidence

  1. ↑ cf. Dinesh C. Gupta: Semiconductor Fabrication: Technology and Metrology . ASTM International, 1989, ISBN 0-8031-1273-4 , pp. 291 .
  2. ↑ Michael Quirk, Julian Serda: Semiconductor Manufacturing Technology: Instructor's Manual ( Memento of September 28, 2007 in the Internet Archive ) (PDF; 1.4 MB). P. 25.
  3. ^ Gary S. May, Simon M. Sze: Fundamentals of Semiconductor Fabrication . Wiley & Sons, 2003, ISBN 0-471-23279-3 , pp. 207 .
  4. ↑ Sami Franssila: Introduction to Microfabrication . John Wiley & Sons, 2010, ISBN 978-0-470-74983-8 , pp. 336 .
  5. ^ Yuzhuo Li: Microelectronic Applications of Chemical Mechanical Planarization . John Wiley & Sons, 2007, ISBN 978-0-471-71919-9 , pp. 349-350 .