Layout draft (electrical engineering)
Under layout design of an electronic circuit ( circuit , multi-chip module , printed circuit board ) is defined as the creation and verification of the geometrical arrangement of the cells or components and their connections. The verification within the layout design comprises i. General checking the designed layout for compliance with all technological and electrical rules.
Layout creation (layout synthesis)
When creating the circuit layout, the network list of a circuit is converted into its real geometric representation using library and technology information. All circuit elements (cells / gates, macro cells, transistors , etc.) are shown in their geometric image (shape, dimensions, level assignment) and their spatial arrangement (placement) and the specific connection structures (wiring) between them are determined. The result is the layout representation of the circuit, which is used after a layout verification to manufacture the assembly (circuit, multi-chip module, circuit board).
Due to its complexity, the creation of the layout is divided into individual sections. In the case of digital circuit or chip design , it is common to carry out the steps of partitioning, floor planning , placement, global and fine wiring and, if necessary, compacting . The essential steps for circuit boards are the placement of the components and the circuit board unbundling .
The automated layout creation for integrated circuits is often referred to as layout synthesis .
Layout verification
The creation of the layout is followed by a comprehensive verification of the layout for its technological feasibility, electrical correctness and electrical functionality.
The DRC ( Design Rule Check ) verifies the feasibility of the layout by checking compliance with the technologically-related design rules in the layout.
The extraction , in which the layout information is processed for verification, is also used to verify the circuit layout. For example, a netlist can be extracted from the layout , which is then checked for equality in the LVS ( Layout Versus Schematic ) with the (original) netlist derived from the circuit diagram in order to determine the electrical correctness of the layout. During the parameter or parasite extraction, their electrical parameters are derived from the geometric properties of the layout structures in order to then use them, including the network list, to validate the electrical properties of the circuit layout.
The ERC ( Electrical Rule Check ) checks the electrical functionality of the layout, e.g. B. compliance with a maximum resistance value between two network connections.
From layout to integrated circuit
The layout information, often in the form of GDSII or OASIS data, is transferred to the facility producing the circuit, the so-called fab or foundry . This process is still called “ tape out ” today, although data is no longer transferred using magnetic tape as it used to be. For this purpose, the layer-specific layout information is first implemented in photolithographic masks in a mask work . These masks are used in the fab to expose the photoresist located on the silicon in technologically precisely defined mapping steps of the layout. The photolithographic masks can thus be used to define areas on the silicon where materials are to be applied, changed or removed. A large number of integrated circuits are produced in parallel on a silicon wafer . The individual, unpackaged circuits, the so-called dies or bare chips, are (pre-) tested on the wafer and marked as “good” or “bad”. Finally, the wafer is sawn into individual dies. The dies marked “good” are connected and packaged in a circuit housing.
From layout to circuit board
The result of the layout design are the so-called Gerber files for circuit board manufacture . For each layer, these describe the coordinates of the polygons that define the conductor tracks, as well as those of the apertures for the photo plotter. In addition, files are required for production that describe the position and diameter of the holes and the coordinates of the circuit board contour or cutouts. These are tool-dependent.
Before production, several circuit boards are usually combined into a so-called batch in order to make the best possible use of the circuit board area available during production.
See also
literature
- J. Lienig: Layout Synthesis of Electronic Circuits - Basic Algorithms for Design Automation ; 2nd edition, Springer (2016), Berlin, Heidelberg, New York, ISBN 978-36-624-9814-9 .
- J. Händschke: Circuit board design - a manual not only for practitioners ; Eugen G. Leuze Verlag (2006), Bad Saulgau, ISBN 3-87480-219-1 .
- A. Kahng, J. Lienig, I. Markov, J. Hu: VLSI Physical Design: From Graph Partitioning to Timing Closure ; Springer (2011), Berlin, Heidelberg, New York, ISBN 978-90-481-9590-9 .
- Ch. Saint, J. Saint: IC Mask Design - Essential Layout Techniques ; McGraw Hill, New York, 2002, ISBN 0-07-138996-2 .