Layout versus Schematic
Layout versus Schematic (LVS) is a step in the layout verification of integrated circuits . It is used toensurethat the layout created matches the original schematic . Here, a net list comparison, for which the carried layout design used original net list is compared to an extracted exclusively from the circuit layout netlist.
The extraction of the netlist from the layout is done using an extracting files. It defines elementary layout structures that, for example, map transistors and vias ( vertical interconnect access , electrical connection between two conductor track levels ), as their detection is necessary for generating net lists. This allows the geometric structures of the layout to be examined to determine which functional units (components and connection structures) they implement. This information allows a network list to be generated exclusively from the circuit layout.