Copacobana

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Copacobana

Copacobana ( Cost-Optimized Parallel Code Breaker ) is an application-specific parallel computer architecture , consisting of Field Programmable Gate Arrays (FPGA). The system was built in 2006 by two working groups at the Universities of Bochum and Kiel . It represents an adequate target system for any parallelizable application with little memory and communication requirements.

background

Cryptanalysis is an important tool for determining the security of the cryptosystems used and disclosed today . The symmetrical and asymmetrical encryption methods are the most widespread, although they can be broken using the brute force method , which involves trying out all possible keys. Security is therefore largely determined by the computational effort required for cryptanalysis and the associated monetary and time costs, provided the cryptosystem does not contain any systematic weaknesses that could be exploited by another form of cryptanalysis.

motivation

For the brute force method, the PC is usually used as the standard architecture with its price-performance ratio. But this comparison is only justified if there is no system with a more favorable price-performance ratio based on the cryptanalysis algorithm . Here the technology of programmable logic circuits is more efficient than the PC. For example, an FPGA of the type Xilinx Spartan-3 1000 400 million keys in the Data Encryption Standard (DES) can compute per second, whereas a PC of the type Intel Pentium 4 with 2 GHz only costs around two million DES keys for about four times the price can calculate. An application-specific integrated circuit (ASIC) would offer an even better price-performance ratio for quantities of around 10,000 or more integrated circuits , but a new system would have to be built for each of the cryptosystems to be analyzed. Both the required number of chips and the construction costs per application put the price advantage into perspective in such a way that the FPGA-based approach shows clear advantages.

Hardware architecture

The development of Copacobana was undertaken with the consistent exhaustion of architectural and technical freedoms in order to achieve the primary goal of the cryptanalysis-related price-performance ratio and the secondary goal of a budget of 10,000 USD. In this way, a parallel, reconfigurable computer , consisting of 120 FPGAs (Xilinx Spartan-3 1000) , was created, in which memory and high-performance intercommunication of the FPGAs was dispensed with for reasons of cost. The power consumption is around 600 W under full load  . The device can be mounted in a standard 19-inch rack and is 3 U high. There is also a Spartan 3-5000 and a Virtex 4 -SX35-based variant, each with 128 FPGAs.

application

Copacobana calculates a complete key search using the Data Encryption Standard (56-bit DES) at a rate of 65 billion DES keys per second. This gives an average time of 6.4 and a maximum time of 12.8 days to find the key. Even if current cryptosystems have such long key lengths that a complete key search is beyond the scope of Copacobana, it is used by means of a reduced key length through extrapolation to determine the cost-related security of current cryptosystems. Furthermore, weak encryption method (eg. As are e-passport ) with Copacobana broken, due to the limited performance of embedded systems still used. Ultimately, Copacobana can generally be used for all parallel applications that are characterized by low memory and communication requirements. Copacobana is now available in several application-optimized versions and scales. So is z. B. the Virtex-4 SX35 based variant suitable to attack Elliptic Curve Cryptography or the algorithms A5 / 1 and / 2 known from GSM .

Offshoot

In 2007, the working groups of the University of Bochum and Kiel founded the spin-off ( "spin-off") SciEngines GmbH , which deals with the sale and development of Copacabana.

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