ARM Cortex-R

ARM Cortex-R is a family of 32-bit processors , built as a Reduced Instruction Set Computer (RISC), based on the ARMv7 architecture . ARM Cortex-R are designed for tough real-time requirements, are usually operated with a real-time operating system (RTOS) optimized for the application and are used, among other things, in safety-critical applications such as control units for airbags or engine controls . Further areas of application for Cortex-R are in data throughput-optimized applications such as control units on hard drives and solid-state drives .

The IP cores developed by ARM Limited are taken over by various licensees for the respective application, as is the case with other ARM cores, and then supplemented by the licensee with additional hardware modules such as input and output interfaces in their own integrated circuits . A licensee is among others the company Texas Instruments which markets the processors under the name Hercules . These Cortex-R can be certified for safety-critical applications according to IEC 61508 and ISO 26262 .

As of the end of 2016, the members of the Cortex-R family include processors with the type designations ARM Cortex-R4 (F), this processor was developed in 2011, the successor models ARM Cortex-R5 (F), ARM Cortex-R7 (F) , ARM Cortex-R8 (F), and the ARM Cortex-R52 (F) developed in 2016. The (F) stands for the integrated floating point unit (FPU).

The adjustments to these processors required for real-time-capable applications include:

• Memory areas that are especially closely connected to the core, so-called English tightly-coupled memory, TCM , which avoids the unpredictable access behavior of caches . Time-critical routines can be stored in these memory areas, which always have exactly the same execution behavior regardless of the states of the cache.
• A time-deterministic interrupt handling .
• Extended exception handling directly in the hardware and independently of the software.
• Extended memory protection in the form of its own English memory protection unit , MPU .
• A memory interface equipped with forward error correction (ECC), which not only recognizes memory errors, but can also correct them to a certain extent.
• Some implementations are also designed as dual-core with the ability to lockstep . The dual core is not used to increase the total computing power, but the identical program is processed in parallel by the two cores and the results are compared in hardware for differences. In this way, hardware failures in the integrated circuit of the CPU can be detected.

See also

• ARM architecture
• ARM Cortex-A
• ARM Cortex-M

Individual evidence

1. ↑ ^{a b} Processors Cortex-R Series. Retrieved March 1, 2018 . 
2. ↑ Hercules ARM Cortex-R microcontrollers. Retrieved March 2, 2018 . 
3. ↑ ARM technical manual: Tightly-coupled memory. Retrieved March 2, 2018 .