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Logo of the I²C bus

I²C , for English Inter-Integrated Circuit , in German spoken as I-Quadrat-C or English I-Squared-C ( ˈaɪ skwɛərd ˈsiː ) or I-2-C ( ˈaɪ tuː ˈsiː ), is a 1982 by Philips Semiconductors (today NXP Semiconductors ) developed serial data bus .

It is mainly used inside the device for communication between different circuit parts, e.g. As between a controller and peripherals - ICs . The original system was developed by Philips in the early 1980s to easily control various chips in televisions . Since the mid-1990s, I²C has also been used by some competitors to designate Philips-compatible I²C systems, including Siemens AG (later Infineon Technologies AG), NEC , STMicroelectronics , Motorola (later Freescale ), Intersil, etc. There are over 1000 in total various ICs from over 50 manufacturers (as of 2014).

Atmel introduced for licensing reasons the designation TWI also used by some other manufacturers today (two-wire interface, English for two-wire interface ) a; technically, TWI and I²C are practically identical. However, the original patent expired on October 1, 2006, so there are no longer any license fees for the use of I²C. I²C is also not a registered trademark of NXP Semiconductors, trademark protection exists only for the logo.


The bus was introduced by Philips in 1982 for internal communication between ICs in e.g. B. CD players and televisions. The MAB8400 microcontroller family , which contained an I²C bus controller, was developed for this purpose. The first standardized specification 1.0 was published in 1992. This supplemented the original standard with 100  kbit / s with a new "fast" mode (fast mode) with 400 kbit / s and expanded the address space by a 10-bit mode, so that instead of the original 112 nodes up to 1136 nodes get supported.

With version 2.0 from 1998 a "high-speed mode" (Hs-mode) with max. 3.4 Mbit / s in addition, with the current and voltage requirements being reduced in this mode. Version 3.0 from 2007 introduced a further mode "Fast-mode Plus" (Fm +) with up to 1 Mbit / s, which, in contrast to Hs-mode, uses the same protocol as the 100 and 400 kbit / s modes.

In 2012, with the specification V.4, an even faster “Ultra Fast-mode” (Ufm) mode was introduced, which supports unidirectional transmission rates of up to 5 Mbit / s. In the same year, some errors in the previous version were corrected with the current version 5. In April 2014 V.6 was released, which again corrected errors.

Bus system

I²C is designed as a master-slave bus. A data transfer is always initiated by a master; the slave addressed via an address reacts to this. Several masters are possible (multi-master operation). If a master component also works as a slave in multimaster operation, another master can communicate with it directly by addressing it as a slave.

Electrical definition

I²C bus with one master and three slaves

Three devices are shown in the diagram on the right. I²C needs two signal lines: clock (SCL = serial clock) and data line (SDA = serial data). Both are located with the pull-up resistors R P to the supply voltage V DD . All devices connected to it have open collector outputs , which, together with the pull-up resistors, results in a wired AND circuit. The high level should be at least 0.7 ×  V DD , and the low level should be at most 0.3 ×  V DD . The series resistors R S at the inputs of the devices, not shown in the figure, are optional and are used as protective resistors . The I²C bus works with positive logic , i. H. a high level on the data line corresponds to a logical “1”, the low level to a “0”.

Clock and conditions of the bus

Time behavior on the I²C bus: between the start signal (S) and the stop signal (P), the data bits B 1 to B N are transmitted.

The bus cycle is always output by the master. A maximum permitted bus cycle is specified for the various modes. As a rule, however, any slower clock rates can be used if they are supported by the master interface. However, some ICs (e.g. analog-to-digital converters ) require a certain minimum clock frequency in order to function properly.

Maximum allowed clock rates
mode Maximum
transfer rate
Standard Mode (Sm) 0.1 Mbit / s bidirectional
Fast Mode (Fm) 0.4 Mbit / s
Fast Mode Plus (Fm +) 1.0 Mbit / s
High Speed ​​Mode (HS mode) 3.4 Mbit / s
Ultra Fast-mode (UFm) 5.0 Mbit / s unidirectional

If the slave needs more time than is specified by the master's clock, it can keep the clock line at "low" between the transmission of individual bytes (clock stretching) and thus brake the master. The specification of some slave components explicitly states that they do not use clock stretching. Accordingly, there are also bus driver components that are designed so that they can only transmit the clock signal in one direction.

Data ( single bits ) are only valid if their logic level does not change during a clock high phase. Exceptions are the start - stop - and Repeated - start signal. The start signal is a falling edge on SDA while SCL is high, the stop signal is a rising edge on SDA while SCL is high. Repeated - Start looks exactly like the start signal.

A data unit consists of 8 data bits = 1  octet (which, depending on the protocol, are interpreted either as a value or as an address) and an ACK bit. This confirmation bit ( acknowledge ) is signaled by the slave through a low level on the data line during the ninth clock high phase (which is still generated by the master) and as NACK (for not acknowledge ) through a high level . The slave has the low level on the data line create, before SCL goes high, other possible participants read otherwise a start - signal .


A standard I²C address is the first byte sent by the master, whereby the first seven bits represent the actual address and the eighth bit (R / W bit) tells the slave whether it should receive data from the master (low: write access) or has to transmit data to the master (high: read access). I²C therefore uses an address space of 7 bits, which allows up to 112 nodes on a bus (16 of the 128 possible addresses are reserved for special purposes).

Every I²C-capable IC has an address (usually by the manufacturer) from which a model-dependent number of the lowest bits (LSB) can be configured individually via special input pins of the IC. This makes it possible to operate several ICs of this type on the same I²C bus without address conflicts. If address conflicts cannot be avoided, the corresponding ICs must be controlled with separate I²C buses or temporarily separated from the bus.

Due to a shortage of addresses, 10-bit addressing was introduced later. It is downwardly compatible with the 7-bit standard by using 4 of the 16 reserved addresses. Both types of addressing can be used at the same time, which allows up to 1136 nodes on one bus.

Transmission protocol

The start of a transmission is indicated by the start signal from the master, followed by the address. This is confirmed by the corresponding slave with the ACK bit. Depending on the R / W bit, data is now written byte by byte (data to slave) or read (data from slave). The ACK when writing is sent by the slave and when reading from the master. The master acknowledges the last byte of a read access with a NACK to indicate the end of the transfer. A transmission is terminated by the stop signal. Alternatively, a can Repeated - Start at the beginning retransmission are sent without the previous transmission with a stop signal to stop.

All bytes are transmitted " Most Significant Bit First".

For the high-speed mode , a master code is first sent in the fast or standard mode before switching to the increased frequency. On the one hand, this signals the high-speed mode and , on the other hand, bus subscribers not suitable for high-speed have the chance to recognize within their specification that they have not been addressed. In multi-master operation, each bus master must use its own master code . This ensures that the bus arbitration (see below) is completed before switching to high-speed mode .

Arbitration in multimaster operation

The arbitration (access control to the bus) is regulated by the specification: The bus is occupied between the start and stop signal. Bus masters must therefore always pay attention to start and stop signals in order to keep track of the bus status. In this way you can wait until the bus is free should a transmission be pending (possibly unexpectedly).

If several bus masters want to start a transaction at the same time, they see the bus as free and start the transfer at the same time. If the masters are at different speeds, the transmission is now initially as fast as the slowest of the bus masters involved, since the clock signal of a slower bus master slows down the faster ones by clock stretching. All bus masters listen to the data they have sent themselves. At the moment when one bus master wants to transmit a "0" and another a "1", the bus line takes on the "0" level (due to the wired-and connection of all bus participants). According to the I²C protocol, at this moment the bus masters with the "1" lose the bus, withdraw and wait for the stop signal to try their luck again. The other bus masters continue until there is only one left. If an inferior bus master module also offers slave services, it must, however, at the same time ensure that the winning bus master is currently trying to address it and is therefore in the process of addressing it.

The procedure goes so far that no arbitration takes place if several bus masters randomly - over several bytes from the beginning to the conclusion of their respective transactions - send identical data to the same slave module: The bus masters concerned do not notice anything about each other - possible clock According to the protocol, stretching by a slower master cannot be distinguished from clock stretching by the slave; the addressed slave module communicates with the relevant bus masters at the same time without being noticed by those involved. This fact must be taken into account and, if it could have a disruptive effect, other remedial measures must be taken.


Serial EEPROM with I²C bus from STMicroelectronics

One of the characteristics of I²C is the fact that a microcontroller can control an entire network of integrated circuits with just two I / O pins and simple software. Buses of this type have been implemented because a not inconsiderable part of the cost of an integrated circuit and the printed circuit board used depends on the size of the housing and the number of pins. A large IC package has more pins, takes up more board space, and has more connections that can fail. All of this increases production and testing costs.

Although slower than newer bus systems, I²C is advantageous for peripheral devices that do not need to be fast because of its low overhead. It is often used for the transmission of control and configuration data. Examples are volume controls, analog-digital or digital-analog converters with a low sampling rate, real-time clocks, small, non-volatile memories or bidirectional switches and multiplexers . Electronic sensors also often have an integrated analog-digital converter with an I²C interface.

Chips can be added to or removed from the bus during operation ( hot plugging ).

I²C is also used as the basis for ACCESS.bus and VESA's monitor data interface ( Display Data Channel , DDC for short ). The SMBus defined by processor manufacturer Intel for the communication of mainboard components is very similar to the I²C bus, most ICs allow operation on both buses.

In the past, the I²C protocol was very important in the chip card sector . The health insurance card used in Germany until the end of 2014 was an I²C card, i. H. A simple I²C- EEPROM was located under the golden contact surfaces of the chip card , which the card reader could read and write using the I²C protocol.


The definition of the I²C bus protocol is quite simple, but also quite susceptible to interference. This fact limits the use to low- interference environments, where neither crosstalk , noise , EMC problems nor contact problems (plugs, sockets) are to be expected. It is also unsuitable for bridging large distances, as is typical for field buses , for example .

However, the bus can be converted to a higher current or voltage level with special drivers, which increases the signal-to-noise ratio and the possible cable length. An even greater signal-to-noise ratio is possible by converting it to the physical layer of the CAN bus, which works with differential open collector signals. Faults in both the SDA and the SCL signals result in incorrectly transmitted data which, especially in the event of faults on the SDA, can often not be recognized. Only in the case of minor, temporary disruptions, e.g. B. well above the signal frequency, the system can be made more stable by means of signal processing .

The actual I²C specification (unlike the SMBus specification) does not contain a timeout ; this can lead to bus subscribers blocking the bus under certain circumstances. If a slave chip just pulls the data line to "0" while the master aborts the transfer (for example by means of a reset), the data line remains at "0" for an indefinite period of time. Thus, the entire I²C bus with all connected participants (chips) remains blocked. Therefore, in the event of a reset, all bus participants should also be reset, if necessary by interrupting the power supply. Alternatively, a bus clear is carried out: The master generates up to nine clock pulses; The data line should then be released at the latest. Even if the slave module is still in the middle of a transmission and the data line is only released because it is currently outputting a "1", it (or its I²C component) is reset by the next start signal. Analog Devices recommends sending a stop signal first.


In 2014 the MIPI Alliance presented an interface called I3C that is downwardly compatible with I²C . It is propagated as the successor to I²C. It contains expansions such as a higher transmission speed (High Data Rate - HDR) and can therefore also replace the Serial Peripheral Interface (SPI) at medium speeds .

See also

  • SMBus : Technically very similar bus, the components are often compatible with the I²C bus.
  • Serial Peripheral Interface : Another serial bus that uses chip-select lines for access to individual ICs, has totem-pole outputs and separate send and receive lines.
  • I²S (Inter-IC Sound): An interface specially designed for the transmission of digital audio data
  • 1-Wire : A serial interface that manages with one data wire that is used both as a power supply and as a transmit and receive line.
  • Display Data Channel (DDC): Serial bus for communication between PC and screen, based on the I²C bus

Web links


  1. Only the signal lines are counted here, not the line for the reference potential (ground line)
  2. The data sheet for AT32UC3A… on page 220 lists small differences in the implementation as an example .

Individual evidence

  1. a b c d e NXP Semiconductors : The I²C-Bus Specification and User Manual, Rev. 6 - 4 April 2014. Original specification (PDF, English; 1.4 MB)
  2. I²C at mikrocontroller.net
  3. For example the I²C isolators ADuM1250 with clock stretching and ADuM1251 without clock stretching
  4. Analog Devices : Implementing an I²C® Reset. (Application Note 686) (PDF)
  5. ^ R. Colin Johnson: MEMS / Sensor Interface I3C Rocks. MIPI Alliance offer improved sensor spec at MEC. EE Times , November 12, 2014, accessed August 2, 2017 .
  6. a b Emmanuel T. Nana: Improved Inter Integrated Circuit (I3C) standard. New serial bus for sensor interface in mobile and electronic equipment. NXP , FTF2016 Technology Forum, May 18, 2016, p. 12 , accessed on August 3, 2017 .