System management bus

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The System Management Bus (abbreviated to SM-Bus , SMBus or SMB ) is a two-wire bus that was developed for module communication (especially for semiconductor ICs). It helps to identify the status of components and to make hardware settings. To save power in portable computers (notebook, PDA, telephone), it makes sense, for example, to switch off expansion slots that are not required or to dim the display.

The bit rate on the SMBus is a maximum of 100 k bit / s. A master on the SMBus takes over bus control (mainly clock generation) when communicating with a slave. If two masters communicate with each other, the addressed master temporarily takes on the role of a slave.

Since the SMBus usually only needs two lines (clock and data line), it can be laid on circuit boards to save space; Likewise, the connected chips only need two pins and therefore fit into smaller chip housings .

An SMBus device can e.g. B. provide manufacturer information, output the model or serial number , display the status of the energy-saving mode, report different types of errors, accept control parameters , return a status or control a display. Since the use of the SMBus requires detailed knowledge of the hardware at hand, it is often neither configurable nor accessible to the user. On some PC motherboards, however, it is accessible via a pin header.

The bus was defined by Intel in 1995 . The standard precisely defines the timing of the bus signals and the electrical connection data. The SMBus is based on the I²C bus protocol from Philips . The voltage levels on the bus may be between 3 V and 5 V and are therefore downward compatible with those of the I²C bus .

The SMBus has an optional, low-active , shared open collector signal (ALERT #) that the slaves can use to trigger an interrupt request from the controller . In the course of processing the interrupt request, the controller queries the triggering slaves using the Alert Response Address Protocol. Each triggering slave identifies itself by attempting to respond with its slave address to read access from a specially reserved address (0C 16 ). During the read access, the triggering slaves carry out an arbitration similar to the I²C multimaster bus arbitration , whereby each slave only deactivates its ALERT signal when it has been able to successfully transmit its address to the controller using the Alert Response Address Protocol . To do this, the controller must repeat the Alert Response Address Protocol until the ALERT signal is no longer active.

SMBus support Microsoft operating systems from Windows 2000 as well as the Open Source - Operating Systems FreeBSD , OpenBSD , NetBSD and Linux .

SMB1 is a common name for a connection on the SM bus.

Web links

source

  1. Data sheet TMP112x High-Accuracy, Low-Power, Digital Temperature Sensors With SMBus and Two-Wire Serial Interface in SOT563, p. 13, Section 7.3.2.5 SMBus Alert Function, online (English, 1 MB)