- the computer structure , i.e. the structure of a computer from functional units (e.g. the ALU , registers ) and their connection structure (e.g. through buses ),
- as well as the computer organization , d. H. the organization of the interaction of the functional units, so that workflows are created which execute commands.
The microarchitecture does not refer to the concrete physical and production-related implementation of a CPU. The microarchitecture is a branch of the computer architecture and thus also of the technical informatics .
The computer organization is the organization of the interaction of all functional units , so that work processes are created which execute the commands of the instruction set . The computer organization is implemented by the control unit . The main functional units of the control unit are:
- The command counter register, it contains the (working) memory address of the currently executed command
- The command decoder :
- With RISC architectures, this consists of switching networks .
- With CISC architectures, the commands are translated by the command decoder into one or more micro-commands (or micro-operations, µops). These microinstructions are stored in the queuing unit. The queuing unit includes a L0 cache (the queue) and the microprogram controller . The microinstructions of the microcode are similar to RISC.
- RISC architectures use an operation control which consists of finite automata . CISC architectures use a microprogram control unit, which also consists of finite automata. The task of both units is to convert commands (commands from the command set at RISC, micro-commands from the queuing unit at CISC) into control signals for the functional units. If available, dynamic scheduling of the commands is also implemented here.
Design of a micro-architecture
It is useful to use a hardware description language to design a microarchitecture .
Performance characteristics of micro-architectures
When optimizing for various performance goals, the programs to be executed, the instruction set, the micro-architecture, the production and their interaction must be taken into account. Despite this complex of topics, there are performance characteristics that depend solely on the micro-architecture, examples are:
It defines the maximum number of instructions in the instruction set that a processor core can process per clock cycle. One differentiates:
- non-scalar processors that do not use pipelining. In any case, these computers process less than one machine command per clock cycle.
- scalar processors that use pipelining . In the best case, these computers process exactly one command per clock cycle.
- superscalar processors that use advanced pipelining. In the best case scenario, these computers process more than one command per clock cycle. All modern desktop computers (2018) are superscalar.
One or more caches are used to accelerate the execution of machine commands . Caches are necessary in order to be able to intercept the meanwhile 2 orders of magnitude difference in speed between processor cores (0.2 ... 0.8 ns / clock) and main memory (45 ... 70 ns) and to enable multiple cores within one CPU. Meanwhile, at least 2 cache levels (ARM) are common, with Intel / AMD 3 cache levels are common. Cache coherence protocols are also used to maintain the consistency of the caches in multi-core processors .
There are multi-core computers , multiprocessor systems and parallel computers used for simultaneous processing of several sequential programs. Modern computers also support parallel computing on one core through extensions in the instruction set architecture, such as multi media extension . However, there are limits to how far an application can be parallelized (see Amdahl's law , Gustafson's law ).
- AMD developer guides
- Intel developer guides
- Detailed descriptions of micro-architectures:
- Austin, Todd .: Computer architecture From digital logic to parallel computers . 6th, updated edition. Pearson Studium an imprint from Pearson Germany, Hallbergmoos 2014, ISBN 978-3-86894-238-5 , p. 320 .