Control unit

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The control unit , also program control unit or control unit ( English control unit , short  CU ), is a functional unit of a processor that controls the sequence of command processing. The control unit performs this task by sending control signals to and from other functional units via the control bus. All activities of the control unit are directly dependent on the CPU cycle.


In addition to the arithmetic logic unit, the control unit is the main component of the processor . The control unit contains the command counter , the command register , the command decoder and the operation control . The task of the control unit is to control all other functional units in the processor and, as a result, to process a machine program . It does this by applying control signals to the control bus (e.g. to select register input / output or ALU operations). On the other hand, the control unit also receives signals from the control bus, in particular the status bits of the ALU. These status bits enable the control unit to execute conditional jump commands (with x86: JZ, JE ...).

The control unit of a computer with "classic" Von Neumann architecture follows the Von Neumann cycle with the phases FETCH, DECODE, FETCH OPERANDS, EXECUTE and WRITE BACK when processing a machine program. The FETCH and DECODE phases are the same for every machine command, the remaining phases are specific to the machine command.

  1. FETCH: The main memory address that is in the command counter is accessed. The data that are located in the main memory at this address are loaded into the command register. The command counter is incremented (+ 1 calculated).
  2. DECODE: The decoder is a switching network that has the contents of the command register as input. The decoder has outputs for every possible machine command (e.g. with x86: ADD, MUL, JMP ...) and for every possible operand (e.g. with x86: eax, ebx, ecx, edx, a memory address ...). He sets these outputs according to the content of the command register. All outputs of the decoder lead to the operation control .
  3. FETCH OPERANDS: The finite automaton that stands for the execution of the machine command in the command register has now been activated in the operation control . Depending on which operands have been selected by the decoder and which machine command it is, either the operands that are needed for the execution of the command are loaded or the EXECUTE phase is started immediately (in the same clock cycle).
  4. EXECUTE: All the necessary data are now available in registers. Depending on the type of machine command, one or more operations are now carried out. The following applies to x86: Simple commands such as MOV, JMP or ADD require little time. Complex commands are MUL and DIV, these require more time depending on the micro-architecture .
  5. WRITE BACK: This phase of command execution only exists in CISC computers. With x86 the following applies: A WRITE BACK phase is only necessary if a command writes back to the main memory, but it is not necessary for the MOV command, because this may already write back to the main memory in the EXECUTE phase.

If no HALT command has been executed, the cycle now starts again.

More modern computers use pipelining , superscalarity , dynamic scheduling ( scoreboarding , the Tomasulo algorithm ), simultaneous multithreading and other methods that complicate the control unit but accelerate the execution of instructions.

See also


  • Jürgen Ortmann: Introduction to PC basics. 8th edition, Addison-Wesley Verlag, Munich 2003, ISBN 3-8273-2102-6 .
  • Wolf-Dieter Haaß: Handbook of the communication networks. Introduction to the basics and methods of communication networks, Springer Verlag Berlin Heidelberg, Berlin Heidelberg 1997, ISBN 978-3-642-63825-1 .

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