Super scalarity

Processor board of a CRAY T3e parallel computer with four superscalar alpha processors

Under superscalar is meant the property of a processor to process multiple instructions from an instruction stream at the same time with a plurality of parallel-working function units. It is a concurrency at the command level, in which the fine-grain concurrency between the individual commands is used. Since Superskalartechnik does not change the instruction set architecture, is also a microarchitecture spoken.

In English, a superscalar processor is also known as a multiple-issue processor . From a technical point of view, superscalarity is a further development of CPU pipelining and is used in high-end processors, and since the Intel Pentium also in standard processors in personal computer technology. Superscalarity is not very common in the field of microcontrollers . ARM addressed this deficiency in 2014 with the Cortex M7 microcontrollers.

The basic principle of the superscalar approach emerged in 1964 at Control Data Corporation (CDC) , which developed the first supercomputer ( CDC 6600 ). The computer architecture of the CDC 6600 already included several functional units working in parallel for different mathematical operations.

There are three types of superscalarity:

Superscalar processors with static scheduling : The number of commands that can be executed in parallel per CPU cycle is not specified, but is determined dynamically by the CPU. Since the scheduling is static, the order of the commands is specified by the compiler ( in-order execution ).
Superscalar processors with dynamic scheduling : The CPU determines which instructions are executed in parallel as well as the order in which this happens ( out-of-order execution ).
VLIW processors ( Very Long Instruction Word ) : These architectures use significantly longer instructions in which the instructions to be executed in parallel are specified. In the IA-64 architecture, this is also called EPIC .

With the help of superscalar processors, the number of commands executed per cycle unit ( Instructions per Cycle , IPC) can be increased. The reason for this is that loading commands and operands usually takes significantly fewer clock units than executing the commands. The latter also depends on the type of commands (addition, multiplication, division, etc.).

The term superscalar is a modification of the term scalar . Scalar processors can execute a maximum of one instruction per clock cycle. Superscalar processors, on the other hand, can execute more than one instruction per clock cycle.

Individual evidence

↑ Cortex-M7 Processor http://arm.com/products/processors/cortex-m/cortex-m7-processor.php
↑ Cortex-M for Beginners - An overview of the Arm Cortex-M processor family and comparison (2017) https://community.arm.com/cfs-file/__key/telligent-evolution-components-attachments/01-2057- 00-00-00-01-28-35 / Cortex_2D00_M-for-Beginners-_2D00_-2017_5F00_EN_5F00_v2.pdf , 2.5 Instructions support in Cortex-M7
^ John Hennessy, David Patterson: Computer Architecture. A quantitative approach. 4th Edition, Morgan Kaufmann Publishers, ISBN 978-0-12-370490-0 , p. 114.

[1] Cortex-M7 Processor http://arm.com/products/processors/cortex-m/cortex-m7-processor.php

[2] Cortex-M for Beginners - An overview of the Arm Cortex-M processor family and comparison (2017) https://community.arm.com/cfs-file/__key/telligent-evolution-components-attachments/01-2057- 00-00-00-01-28-35 / Cortex_2D00_M-for-Beginners-_2D00_-2017_5F00_EN_5F00_v2.pdf , 2.5 Instructions support in Cortex-M7

[3] John Hennessy, David Patterson: Computer Architecture. A quantitative approach. 4th Edition, Morgan Kaufmann Publishers, ISBN 978-0-12-370490-0 , p. 114.