The MIPS architecture ( English M icroprocessor without i nterlocked p ipeline s day ; German as "microprocessor without folded pipeline stages") is an instruction set architecture in RISC style, which from 1981 by John L. Hennessy and his colleagues at Stanford University was developed. The further development took place from 1984 at the newly founded company MIPS Computer Systems Inc., later MIPS Technologies , and today belongs to the US technology company Wave Computing , based in Silicon Valley .
MIPS was originally a 32-bit architecture, the 64-bit expansion followed in 1991 and was introduced with the R4000. Many RISC architectures from this time influenced each other, including Sun SPARC , DEC's Alpha processor or Hewlett-Packard's PA-RISC . The MIPS architecture uses the register / register execution model.
From February 2013, the MIPS architecture was further developed and marketed by the British company Imagination Technologies . In 2017, the MIPS division, together with the PowerVR division, was sold to the Chinese investment company Canyon Bridge Capital Partners and was most recently owned by Tallwood Venture Capital . Since June 2018, the MIPS architecture is one of the 2010 founded on AI specialized start-ups Wave Computing, which with the acquisition of the development of AI and Deep Learning would further advance by the combination of both technologies. For this purpose, the MIPS Open Initiative was launched at the end of 2018 and it was announced that the MIPS architecture would be placed under an open source license at the beginning of 2019 .
MIPS processors were from Silicon Graphics in Unix - Workstations (. Eg SGI Indigo ) and Unix servers (such as SGI. Origin2000 ) used. In the past, other workstation manufacturers such as B. the Digital Equipment Corporation (DEC) machines with MIPS processors, so z. B. the DECstation family (2100, 3100, 5000) and the DECsystem under the Ultrix operating system . Siemens and SNI equipped their servers of the RM series with MIPS processors from the R4000, R5000 and R10000 families, Sun used processors from the R5000 family in several server models from the Cobalt Qube and RaQ series. There have been attempts to accelerate MIPS processors with the help of ECL technology . The type R6000 was used for this, ultimately an ECL version of the R3000. This type of processor was used in computers of the CDC 4680 type from Control Data Corporation .
In the early 1990s, MIPS Computer Systems Inc. began licensing its microprocessor designs to third parties . From the mid-1990s, the MIPS architecture found its way into the video game consoles Nintendo 64 (1996), PlayStation (1994), PlayStation 2 (2000) and PlayStation Portable (2004).
CPUs with MIPS architecture are still often used in the construction of e.g. As network routers , automotive navigation systems , digital receivers , set-top boxes and digital SLR cameras embedded . The use of the MIPS-based processor cores within these device classes takes place in the context of one-chip systems (SoCs). Imagination Technologies offers manufacturers both ready-made IP cores and an architecture license.
The Institute of Computing Technology (ICT) of the Chinese Academy of Sciences acquired an architecture license for the development of the MIPS-compatible Loongson CPU in 2009. The Loongson 3B model forms the microprocessor basis for the Chinese supercomputer Dawning 6000.
An instruction in these processors is processed in several stages in a pipeline , so that several instructions in different processing steps (e.g. fetch command, decode instruction and fetch operands, execute instructions with operands, read or write main memory and write back the result) are in the processor at the same time can. If a subsequent command relies on the result of a previous one, the subsequent command may have to be stopped until the result is available. This is usually achieved through locks (“stalls”). Another way of processing such data hurdles is so-called "forwarding", in which the calculation results required for the following instruction are passed to the next instruction immediately after the calculation, instead of fetching the value from a register in the next possible cycle.
The MIPS architecture dispenses with such locks and requires the assembly language programmer or compiler to take appropriate measures, such as re-sorting or inserting zero operations (NOP). This allows the architecture to be kept simple. It has been shown, however, that the machine code was inflated by the NOP commands to be inserted in such a way that the hit rate in the command cache introduced later was reduced. This in turn led to performance losses, which should actually be avoided by the original waiver of interlocking. Measures were therefore implemented in the subsequent MIPS versions that enable the program to run without taking the pipeline stages into account. The abbreviation “MIPS” has since lost its real meaning.
Another mechanism used to speed up the MIPS architecture is what is known as superpipelining. In contrast to spatially parallel architectures (e.g. VLIW processors), a temporal parallelism of the command processing is achieved here by dividing the command pipeline into more stages. This creates a finer subdivision of the assembly line. The stages of the pipeline have a shorter turnaround time in this way, and therefore the clock rate can be increased. Superpipelining was first implemented in the MIPS-R4000 processors.
process in µm
|R2000||8.3 ... 16.7||1985||2.0||0.11||80||?||?||?||32||64||-|
|R2000A||12.5 ... 16.7||1988||2.0||0.11||80||?||?||?||32||64||-|
|R3000A||25 ... 40||1989||1.2||0.11||66.12||145||4th||?||64||64||-|
|R4400||150 ... 250||1992||0.6||2.3||186||179||15th||5||16||16||1|
|R5000||150 ... 200||1996||0.35||3.7||84||223||10||3.3||32||32||1|
|R7000||250 ... 600||2000||0.13||?||?||304||2-3||3.3 (io) / 1.2 (int)||16||16||0.25|
|R8000||75 ... 90||1994||0.5||2.6||299||591||30th||3.3||16||16||1… 8|
|R10000||150 ... 270||1995||0.35||6.8||299||599||30th||3.3||32||32||0.5 ... 16|
|R12000||300 ... 400||1998||0.18-0.25||6.9||204||600||20th||2.3||32||32||0.5 ... 16|
|R14000||500 ... 600||2001||0.13||7.2||204||527||17th||1.5||32||32||0.5 ... 16|
|R16000||700||2002||0.11||?||?||?||20th||1.5||32||32||0.5 ... 16|
|R16000A||800 ... 1000||2004||0.11||?||?||?||?||1.5||32||32||0.5 ... 16|
- QtSpim - latest version of Spim, cross-platform user interface.
- MARS (MIPS Assembler and Runtime Simulator) is a MIPS32 emulator written in Java at Missouri State University .
- JPCSP is a MIPS R4000 (Allegrex) emulator based on the Java programming language, which primarily emulates PSP software .
- Unicorn is a QEMU based emulator that offers interfaces for many modern programming languages (including C, Python and Java).
- David A. Patterson, John L. Hennessy: Computer Organization & Design, The Hardware / Software Interface . 4th edition. Morgan Kaufmann Publishers, San Francisco 2008, ISBN 0-12-374493-8 .
- John L. Hennessy, David A. Patterson: Computer Architecture - A Quantitative Approach . 3. Edition. Morgan Kaufmann Publishers, San Francisco 2003, ISBN 1-55860-724-2 .
- MIPS processors: Pictures and descriptions on cpu-collection.de
- MIPS Technologies, Inc.
- Patterson & Hennessy - Appendix A (PDF, 483 KiB)
- MIPS architecture overview. Retrieved May 27, 2012 .
- Benjamin Kraft: Imagination Technologies sold to Chinese investor group. In: Heise online . September 24, 2017 . Retrieved June 17, 2018.
- Bernd Mewes: AI specialist Wave Computing buys MIPS. In: Heise online . June 16, 2018 . Retrieved June 17, 2018.
- Alexandra Kleijn: Processor architecture: MIPS becomes open source. In: Heise online . December 18, 2018 . Retrieved December 18, 2018 .; Quote: "The architecture of the MIPS-CPU will come under an open source license in early 2019 and will be further developed as part of the MIPS Open initiative."
- Andreas Stiller: Processor Whisper - From MIPS and MIPS In: c't - magazine for computer technology , October 9, 2010.
- courses.missouristate.edu MARS (MIPS Assembler and Runtime Simulator)
- Unicorn: Unicorn - The ultimate CPU emulator. Retrieved September 12, 2017 .