List of Intel microprocessors

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This is a list of Intel PC microprocessors, sorted by time . For a list of math coprocessors , see the list of x86 coprocessors . See also Intel Processor Model Numbers .

1970-1979

4004

  • Introduction date: November 15, 1971
  • Processor clock: 740 kHz (0.09 MIPS)
  • Bus width: 4 bits
  • Transistors / manufacturing technology: 2300 at 10 µm (PMOS)
  • Addressable memory:

The Intel 4004 was the first mass-produced microprocessor in the world. It was originally an order development as part of a desktop computer project for the Busicom company . Intel bought back the very generic CPU design and marketed it.

4040

  • Introduction date: November 1974
  • Processor clock: 740 kHz (0.09 MIPS)
  • Bus width: 4 bits
  • Transistors / manufacturing technology: 3000 at 10 µm (PMOS)
  • Addressable memory:
    • Data storage: 640 nibbles
    • Program memory: 4 KiB

The Intel 4040 was an improved version of the 4004 with interrupts , an extended set of commands and registers.

8008

  • Implementation date: April 1972
  • Processor clock:
    • 500 kHz (0.05 MIPS)
    • 800 kHz (0.08 MIPS) (8008-1)
  • Bus width: 8 bits
  • Transistors / manufacturing technology: 3500 at 10 µm (PMOS)
  • Addressable memory: 16 KiB

The Intel 8008 was used in terminals, calculating machines and packaging machines, for example. The development was started together with the 4004 for the Datapoint 2200 .

8080

  • Implementation date: April 1974
  • Processor clock:
    • 2 MHz (8080A)
    • 2.5 MHz (8080A-2)
    • 3.125 MHz (8080A-1)
  • Bus width: 8 bits
  • Transistors / manufacturing technology: 6000 at 6 µm ( NMOS )
  • Addressable memory: 64 KiB

The Intel 8080 was a long time non-standard CPU with many applications. It was about 10 times the speed of an 8008 and was first widely used in industry - for example in cash registers, traffic lights, bank terminals, weighing systems, controls, but also in cruise missiles . This CPU also became very popular in the hobby area, for example in the Altair 8800 or through the CP / M operating system .

8085

  • Introduction date: March 1976
  • Processor clock: 3 MHz (0.37 MIPS) later also 5 MHz
  • Bus width:
    • Data bus: 8 bit
    • Address bus: 16 bit
  • Transistors / manufacturing technology: 6500 at 3 µm (NMOS)
  • Addressable memory:

The 8085 is a further developed one-chip version of the 8080 CPU, with which Intel was no longer able to build on the popularity of the 8080. The Z80 from Zilog took over the legacy of the 8080 . However, thousands of control units for slot machines from the ADP-Gauselmann Group (keyword "Merkur-Sonne") were equipped with the 8085. There he rendered loyal service for many years, until it was gradually replaced by the Motorola 68000 and serial shift registers around 1992 .

8086

  • Implementation date: June 8, 1978
  • Processor clock:
    • 5 MHz (8086)
    • 8 MHz (8086-2)
    • 10 MHz (8086-1)
  • Bus width:
    • Data bus: 16 bit
    • Address bus: 20 bits
  • Transistors / manufacturing technology: 29,000 at 3 µm (NMOS)
  • Addressable memory: 1 MiB
  • theoretical memory bandwidth: 2.5 MByte / s (8086) to 5 MByte / s (8086-1)

It was used for example in the Schneider-PC 1640 and many other replicas of IBM PC , in the communication technology (. Eg PBXs ) in controls (u. A. In the space shuttle of NASA ). At the symbolic level ( mnemonics , operand format, addressing types ) the command set is based on that of the 8080 to enable easy porting . A segmentation is used to expand the address space to 1 MiB , since only 64 KiB can be addressed directly with 16 bits.

8088

  • Implementation date: June 1, 1979
  • Processor clock:
    • 5 MHz (8088)
    • 8 MHz (8088-2)
  • Bus width:
    • Data bus: 8 bit
    • Address bus: 20 bits
  • Transistors / manufacturing technology: 29,000 at 3 µm (NMOS)
  • Addressable memory: 1 MiB
  • theoretical memory bandwidth: 1.25 MByte / s (8088) to 2 MByte / s (8088-2)

Variant of the 8086 with external 8-bit data bus. From the programmer's point of view, the 8088 behaves like an 8086, but since 8-bit technology was widespread and relatively inexpensive in the late 1970s, the “narrower” data bus of the 8088 should allow the construction of cost-effective systems with “8086 technology” . The 8088 was mainly used in the IBM PC and its replicas, telephone systems, controls, etc. v. m. used.

1980-1989

80186

  • Implementation date: 1982
  • Processor clock:
    • 6 MHz
    • 16 MHz
  • Bus width:
    • Data bus: 16 bit
    • Address bus: 20 bits
  • Transistors / manufacturing technology:
  • Addressable memory: 1 MiB

The Intel 80186 was mainly used in embedded systems , rather seldom in desktop computers of the IBM class (e.g. in the Siemens PCD, Triumph Adler P50 / P60, Tandy 2000, Philips Yes, MAD computer). It contains a slightly improved 8086 core with additional commands, as well as two timers, a DMA and an interrupt controller . It was later renamed iAPX186 .

80188

  • Implementation date: 1982
  • Processor clock:
    • 6 MHz
    • 16 MHz
  • Bus width:
    • Data bus: 8 bit
    • Address bus: 20 bits
  • Transistors / manufacturing technology:
  • Addressable memory:

Like the 80186, but with an external data bus with an 8-bit width, thus reducing costs because the additional chips required were cheaper.

80286

  • Implementation date: February 1, 1982
  • Processor clock:
    • 6 MHz (0.9 MIPS)
    • 8 MHz (1.5 MIPS)
    • 10 MHz
    • 12 MHz
    • 12.5 MHz (2.66 MIPS)
    • 16 MHz
  • Bus width:
    • Data bus: 16 bit
    • Address bus: 24 bit
  • Transistors / manufacturing technology: 134,000 at 1.5 µm
  • Addressable memory: 16 MiB
  • Theoretical memory bandwidth: 6 MByte / s (6 MHz) to 25 MByte / s (25 MHz)

The 80286 had a new operating mode ( Protected Mode ), which enables memory protection for multitasking operating systems. It reaches three to six times the speed of the 8086 and was mainly used in PC clones. He can search the Encyclopædia Britannica in 45 seconds.

i386 DX

  • Introduction date: October 17, 1985
  • Processor clock:
    • 16 MHz (5.4 MIPS)
    • 20 MHz (6.8 MIPS)
    • 25 MHz (8.5 MIPS)
    • 33 MHz (11.4 MIPS) (max.clock of 386 CPUs from Intel, 40 MHz only from third-party manufacturers)
  • Bus width:
    • Data bus: 32 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 275,000 at 1 µm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 GiB
  • Theoretical memory bandwidth: 32 MByte / s (16 MHz) to 66 MByte / s (33 MHz)

The i386DX was the first x86 processor with a 32-bit bus width. It has a revised and expanded memory protection (32-bit Protected Mode ). It also supports virtual memory and virtual 8086 mode. Paging , a linear address space and access protection make porting Unix systems easier . It was mainly used for desktop computers.

i386 SX

  • Introduction date: June 16, 1988
  • Processor clock:
    • 16 MHz (2.5 MIPS)
    • 20 MHz (Intel only delivered the i386SX with 16 MHz, 20 MHz boards existed and were 25% overclocked)
    • 25 MHz
  • Bus width:
    • Data bus: 16 bit
    • Address bus: 24 bit
  • Transistors / manufacturing technology: 275,000 at 1 µm
  • Addressable memory: 16 MiB
  • Virtual memory : 256 GiB
  • Theoretical memory bandwidth: 16 MByte / s (16 MHz) to 20 MByte / s (20 MHz)

The smaller bus width of the i386SX reduced costs, as 80286 peripherals could still be used. On the software side it is completely compatible with the i386DX (with the restriction to a smaller address space), but has a shorter command queue than the i386DX. It was used in desktop PCs and portable computers in the lower price segment.

i486DX

  • Introduction date: April 10, 1989
  • Processor clock:
    • 25 MHz (20 MIPS)
    • 33 MHz (27 MIPS)
    • 50 MHz (41 MIPS)
  • Data and address bus: 32 bit
  • Transistors / manufacturing technology: 1.2 million at 1 µm (50 MHz: 0.8 µm)
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Theoretical memory bandwidth: 100 MByte / s (25 MHz) to 200 MByte / s (50 MHz)

The i486 is the first Intel processor to have an on-chip L1 cache and a math coprocessor ( FPU ). It has 50 times the speed of the 8088 and was mainly used in servers and desktop computers.

1990-1994

80386SL

  • Implementation date: October 15, 1990
  • Processor clock:
    • 20 MHz (4.2 MIPS)
    • 25 MHz (5.3 MIPS)
  • Bus width:
    • Data bus: 16 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 275,000 at 1 µm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

First processor specially designed for portable computers (low power consumption). Highly integrated, contains cache, bus and memory controllers.

i486SX

  • Implementation date: April 22, 1991
  • Processor clock:
    • 16 MHz (13 MIPS) (?)
    • 20 MHz (16.5 MIPS)
    • 25 MHz (20 MIPS)
    • 33 MHz (27 MIPS)
  • Data and address bus: 32 bit
  • Transistors / manufacturing technology: 1.2 million at 1 µm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Theoretical memory bandwidth: 80 MByte / s (20 MHz) to 132 MByte / s (33 MHz)

Corresponds to the i486DX, but with the missing math coprocessor (FPU) and was used in the entry-level segment of the 486 desktop PC. It can be expanded with the i487 coprocessor.

i486DX2

  • Implementation date: March 3, 1992
  • Processor clock:
    • 50 MHz (41 MIPS)
    • 66 MHz (54 MIPS)
  • Data and address bus: 32 bit
  • Transistors / manufacturing technology: 1.1 million at 0.8 µm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Theoretical memory bandwidth: 100 MByte / s (50 MHz) to 132 MByte / s (66 MHz)

Used for fast but inexpensive desktop PC. The processor works internally at twice the frequency of the external bus.

i486SL

  • Implementation date: November 9, 1992
  • Processor clock:
    • 20 MHz (15.4 MIPS)
    • 25 MHz (19 MIPS)
    • 33 MHz (25 MIPS)
  • Bus width:
    • Data bus: 32 bit
    • Address bus: 24 bit
  • Transistors / manufacturing technology: 1.4 million at 0.8 µm
  • Addressable memory: 64 MiB
  • Virtual memory : 64 TiB

Used in notebook PCs.

Pentium (P5)

  • Implementation date: March 3, 1993
  • Processor clock:
    • 60 MHz (100 MIPS)
    • 66 MHz (112 MIPS)
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 3.1 million at 0.8 µm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Theoretical memory bandwidth: 480 Mbytes / s (60 MHz) to 528 Mbytes / s (66 MHz)

Five times the speed of the 33 MHz 486DX processor thanks to the superscalar architecture used in desktop PCs. Internal with RISC core; planned extensions for multiprocessor operation only relevant later. CPUID identification now enables special variants in faster succession.

Intel DX4

  • Implementation date: March 7, 1994
  • Processor clock:
    • 75 MHz (53 MIPS)
    • 100 MHz (70.7 MIPS)
  • Data and address bus: 32 bit
  • Transistors / manufacturing technology: 1.6 million at 0.6 µm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Theoretical memory bandwidth: 100 MByte / s (75 MHz) to 133 MByte / s (100 MHz)

Used in fast entry-level desktop PCs and mid-range notebooks. The system clock was a third (not a quarter!) Of the processor clock, i.e. 25 or 33 MHz.

Pentium (P54C)

  • Implementation date: March 7, 1994
  • Processor clock: 75, 90, 100, 120, 133, 150, 166, 200 MHz
  • Processor socket : socket 5 , socket 7
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 3.2 million at 0.6 µm or 0.35 µm (BiCMOS)
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Theoretical memory bandwidth: 400 MByte / s (75 MHz) to 528 MByte / s (100/133/166/200 MHz)

1995-1999

Pentium Pro (P6)

  • Implementation date: November 1, 1995
  • Base 8
  • Processor clock:
    • 133 MHz (only as a pre-production model), bus clock at 2 × 66 MHz
    • 150 MHz bus clock at 2.5 × 60 MHz
    • 166 MHz bus clock at 2.5 × 66 MHz
    • 180 MHz bus clock at 3 × 60 MHz
    • 200 MHz bus clock at 3 × 66 MHz
  • Internal L1 cache: 8 + 8 KiB (data + instructions)
  • Internal L2 cache with full CPU clock:
    • 256 kiB L2 cache (all processor frequencies)
    • 512 kiB L2 cache (from 166 MHz)
    • 1024 kiB L2 cache (only 200 MHz)
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 36 bits
  • Transistors / manufacturing technology: 5.5 million at 0.6 µm or 0.35 µm
  • Addressable memory: 64 GiB (depending on internal L2 cache)
  • Virtual memory : 64 TiB

Pentium II OverDrive for Pentium Pro (P6T)

  • Implementation date: March 3, 1997
  • Base 8
  • Processor clock:
    • 300 MHz bus clock 5 × 60 MHz
    • 333 MHz bus clock rate 5 × 66 MHz
  • Internal L1 cache:
    • 16 + 16 kiB (data + instructions)
  • Internal L2 cache with full CPU clock:
    • 512 kiB L2 cache
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 36 bits
  • Transistors / manufacturing technology:
  • Addressable memory: 64 GiB
  • Virtual memory : 64 TiB

Pentium MMX (P55C)

  • Implementation date: January 8, 1997
  • Processor clock: 133, 150, 166, 200, 233 MHz
  • Processor socket : socket 7
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 4.5 million at 0.35 µm, later 0.28 µm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • theoretical memory bandwidth: 528 MByte / s (all)

Introduction of MMX technology and enlargement of the level 1 cache from 16 KiByte to 32 KiByte to increase performance

Pentium II (Klamath)

  • Implementation date: May 7, 1997
  • Processor clock: 233, 266, 300 MHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 9 million at 0.35 µm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • theoretical memory bandwidth: 528 MByte / s (all)

The Pentium II has the microarchitecture of the Pentium Pro , which has been somewhat improved and also expanded to include the MMX instruction set. The Klamath was even made in the same technology as the Pentium Pro, but - as u. a. his successors Deschutes and Katmai too - delivered in a more cost-effective plug-in module.

Mobile Pentium MMX (Tillamook)

  • Implementation date: September 8, 1997
  • Processor clock: 166, 200, 233, 266, 300
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 4.5 million at 0.25 µm
  • Addressable memory: 4 GiB
  • theoretical memory bandwidth: 528 MByte / s (all)

Pentium II (Deschutes)

  • Implementation date: April 15, 1998
  • Processor clock:
    • FSB -66 models: 266, 300, 333 MHz
    • FSB-100 models: 350, 400, 450 MHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 9 million at 0.25 µm (models with 266–333 MHz 0.35 µm)
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • theoretical memory bandwidth: 528 MByte / s (all)

The Deschutes was the first processor called "Pentium", which was also available in a variant with a 100 MHz bus clock.

Mobile Pentium II

  • Implementation date: April 2, 1998
  • Processor clock: 266 MHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology:
  • Addressable memory: 4 GiB
  • theoretical memory bandwidth: 528 MByte / s (all)

On a Deschutes basis.

Celeron (Covington)

  • Implementation date: April 15, 1998
  • Processor frequencies: 266 and 300 MHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology:
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • theoretical memory bandwidth: 528 MByte / s (all)

The first Celeron processor uses the core of the first Pentium II variant called Deschutes . However, it lacks the L2 cache, which significantly reduces performance. Since the L2 was not implemented on the motherboard like the Pentium MMX, it could not even hold its own against the lower clocked and cheaper Pentium MMX in many areas of application . The floating point performance, however, was significantly better than with the Pentium MMX.

Pentium II Xeon (Drake)

  • Implementation date: June 29, 1998
  • Processor clock: 400, 450 MHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 7.5 million transistors at 0.25 µm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • theoretical memory bandwidth: 800 MByte / s (all)

The first Xeon processor has a 512, 1024 or 2048 KiB L2 cache. The 2048 KiB variant was only available for the 450 MHz model.

Celeron (Mendocino)

  • Implementation date: August 24, 1998
  • Processor clock: 300-533 MHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology:? Transistors at 0.25 µm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • theoretical memory bandwidth: 528 MByte / s (all)

First Intel processor with an integrated L2 cache in the processor die . It was a good economic compromise between the original Celeron and Pentium II. Later the Celeron was also sold in the cheaper Socket 370 housing, since slot 1 was no longer necessary due to the integrated L2 cache. This processor in the PPGA socket version was very popular. B. on the motherboard ABIT BP6 was suitable as an inexpensive two-processor system. All of the following Celeron cores are deprived of this ability.

Pentium III (Katmai)

  • Implementation date: February 26, 1999
  • Processor clock: 450, 500, 533, 550 and 600 MHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 9.5 million at 250 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Theoretical memory bandwidth: 800 MByte / s (450/500/550/600 MHz), 1067 MByte / s (533/600 MHz), the 600 MHz type was available with both the FSB 100 and the FSB 133.

Streaming SIMD extensions. For the first time with processor GUID (which raised data protection concerns).

Pentium III Xeon (Tanner)

  • Implementation date: March 17, 1999
  • Processor clock:
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology:
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Used in business PCs, two-, four- and eight-way (and higher) servers and workstations.

Pentium III Xeon (Cascades)

  • Implementation date: October 25, 1999
  • Processor clock:
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology:
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Used for two-way servers and workstations.

Pentium III (E series, Coppermine)

  • Implementation date: October 25, 1999
  • Processor clock:
    • 100 MHz FSB types (E series): 550, 600, 650, 700, 750, 800, 850, 900 MHz, 1 GHz, 1.1 GHz
    • 133 MHz FSB types (EB series): 533, 600, 667, 733, 800, 866, 933 MHz, 1 GHz, 1.13 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 28.1 million at 180 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Theoretical memory bandwidth: 800 MByte / s (E series), 1067 MByte / s (EB series)

First Intel processor in 180 nm production. The Coppermine has an on-chip L2 cache (“Advanced Transfer Cache”), which compared to its predecessor, the Katmai, has been reduced from 512  KiB to 256 KiB, but a much larger one due to a revision of the L2 cache interface Throughput. In most cases it is even a little faster than its predecessor.

2000-2004

Celeron (Coppermine-128)

  • Implementation date: March 29, 2000
  • Processor frequencies:
    • 66 MHz FSB types: 533, 566, 600, 633, 667, 700, 733, 766 MHz
    • 100 MHz FSB types: 800, 850, 900, 950, 1000, 1100 MHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 28.1 million at 180 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Theoretical memory bandwidth: 533 MByte / s (66 MHz FSB), 800 MByte / s (100 MHz FSB)

Pentium 4 (Willamette)

  • Implementation date: November 2000
  • Processor clock: 1.3–2 GHz in 100 MHz steps
  • Processor socket: So423 (later also So478)
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 42 million at 180 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • theoretical memory bandwidth: 3200 MByte / s

Pentium III (Tualatin-256, Desktop-Tualatin)

  • Implementation date: June 2001
  • Processor clock: 1.0 GHz, 1.13 GHz, 1.2 GHz, 1.26 GHz, 1.33 GHz, 1.4 GHz
  • Processor socket : Socket 370
  • Design: FC-PGA2
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 44 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

First 130 nm Intel processor . 1.25 V instead of 1.5 V bus voltage (AGTL instead of AGTL + level), which is why the Pentium III with Tualatin core only runs on motherboards with suitable chipsets without an adapter, e.g. B. the Intel i815 (B-Step) or the VIA 694T.

Itanium (Merced)

  • Implementation date: June 2001
  • Processor clock: 733 MHz, 800 MHz
  • Cache: external, max. 4 [MiB]
  • Bus width: 64 bit
  • Transistors / production technology: 25.4 mill (plus L3 cache) 0.18 µm
  • Addressable memory: 64 GiB
  • The Intel Itanium is a 64-bit microprocessor that was jointly developed by Hewlett-Packard and Intel. The development goal was a high-performance architecture of the “post- RISC era” using a modified VLIW design called Explicitly Parallel Instruction Computing or EPIC for short. The Itanium's native instruction set is IA-64 . The commands of the older x86 processors can be only in one (very slow) Firmware - emulation mode to run. There are also extensions for easier migration of processors from the PA-RISC family.

Pentium III -S (Tualatin-512, Server-Tualatin)

  • Implementation date: July 2001
  • Processor clock: 1.13 GHz, 1.26 GHz, 1.4 GHz
  • Processor socket : Socket 370
  • Design: FC-PGA2
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 44 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Pentium 4 (Northwood)

  • Implementation date: July 2001
  • Processor clock: 1.6-3.4 GHz
  • Processor socket: Socket 478
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 55 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Celeron (Tualatin)

  • Implementation date: October 2, 2001
  • Processor frequencies: 1100, 1200, 1300, 1400, 1500 MHz
  • Design: FC-PGA2
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 44 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Like the Pentium III with the Tualatin core in the desktop version, the Tualatin Celeron has 256  KiB L2 cache, but is only clocked with 100 MHz FSB.

Pentium 4 M (Northwood)

  • Implementation date: March 4, 2002
  • Processor clock: 1.4-3.0 GHz
  • Processor socket: Socket 479
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • CPU cash up to 1024 kb
  • Transistors / manufacturing technology: 55 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Celeron (Willamette-128)

  • Implementation date: May 15, 2002
  • Processor clock: 2.0 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 42 million at 180 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Celeron (Northwood-128)

  • Implementation date: September 18, 2002
  • Processor clock: 1.7-2.6 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 55 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Celeron notebook processor (Northwood-256)

  • Implementation date: September 2002
  • Processor clock: 1.0-2.5 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 55 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Pentium M (Banias)

  • Implementation date: March 2003
  • Processor clock: 0.9-1.7 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 77 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Pentium 4 Mobile (Northwood)

  • Implementation date: June 12, 2003
  • Processor clock: up to 2.4 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 55 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Celeron M (Banias-512)

  • Implementation date: January 6, 2004
  • Processor clock: up to 1.5 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 77 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Pentium 4 (Prescott)

  • Implementation date: February 2, 2004
  • Processor clock: 2.8-3.8 GHz
  • Cache: 1 MiB
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 125 million at 90 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • theoretical memory bandwidth: 6400 MByte / s

First processor in 90 nm production.

Pentium 4 Extreme Edition (Gallatin)

  • Implementation date: February 2, 2004
  • Processor clock: 3.2-3.73 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 178 million at 130 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Pentium M (Dothane)

  • Implementation date: May 2004
  • Processor clock: 1.0-2.26 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 140 million at 90 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Celeron D (Prescott-256)

  • Implementation date: June 24, 2004
  • Processor clock: 2.13 - 3.33 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 125 million at 90 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Mobile Pentium 4 (Prescott)

  • Implementation date: June 2004
  • Processor clock: 2.8-3.46 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 125 million at 90 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Celeron M (Dothan-1024)

  • Implementation date: July 2004
  • Processor clock: 1.3-1.7 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 144 million at 90 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

2005-2008

Pentium 4 (Prescott 2M)

  • Implementation date: February 2005
  • Processor clock:
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 169 million at 90 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Pentium 4 Extreme Edition (Prescott 2M)

  • Implementation date: February 2005
  • Processor clock: 3.2-3.7 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 169 million at 90 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Pentium D (Smithfield)

  • Implementation date: April 19, 2005
  • Processor clock: 2.66-3.67 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 230 million at 90 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Pentium Extreme Edition (Smithfield)

  • Implementation date: April 19, 2005
  • Processor clock:
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 230 million at 90 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Pentium Extreme Edition (Presler)

  • Implementation date: December 27, 2005
  • Processor clock:
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 376 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

First processor in 65 nm production.

Pentium 4 (Cedar Mill)

  • Implementation date: January 5, 2006
  • Processor clock: 3.00 to 3.80 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 188 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Pentium D (Presler)

  • Implementation date: January 5, 2006
  • Processor clock: 2.8-3.6 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 376 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Core Solo (Yonah)

  • Implementation date: January 2006
  • Processor clock: 1.50-1.66 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 151.6 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Core Duo (Yonah)

  • Implementation date: January 2006
  • Processor clock: 1.5 to 2.33 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 151.6 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Celeron M (Yonah-1024)

  • Implementation date: April 2006
  • Processor clock: 1.20 to 1.73 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 151 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Celeron D (Cedar Mill-512)

  • Implementation date: June 2006
  • Processor clock: 1.20 to 1.73 GHz or 2.13 to 3.20 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 188 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Core 2 Duo (Allendale)

  • Implementation date: July 27, 2006
  • Processor clock: up to 2.40 GHz
  • Cache: L1 32 + 32 KiB / L2 2x1 MiB
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 64 bits of which 36 can be used
  • Transistors / manufacturing technology: 167 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Core 2 Duo (Conroe)

  • Implementation date: July 27, 2006
  • Processor clock: up to 3 GHz
  • Cache: L1 32 + 32 KiB / L2 2x2 MiB
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 291 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Base: 775

Core 2 Duo (Merom)

  • Implementation date: July 27, 2006
  • Processor clock: up to 2.66 GHz
  • Cache: L1 32 + 32 KiB / L2 2x2 MiB
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 291 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB
  • Socket: 479 or P

Core 2 Extreme (Conroe XE)

  • Implementation date: July 27, 2006
  • Processor clock: up to 3 GHz
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 32 bit
  • Transistors / manufacturing technology: 291 million at 65 nm
  • Addressable memory: 4 GiB
  • Virtual memory : 64 TiB

Core 2 Extreme Quad-Core (Kentsfield)

  • Implementation date: Nov. 14, 2006
  • Processor clock: 2.66 GHz (Core 2 Extreme QX6700), 2.93 GHz (Core 2 Extreme QX6800), 3 GHz (Core 2 Extreme QX6850)
  • Same data as Core 2 Extreme , but with two dual-core The in a housing ( multi-chip module ), a total of four processor cores

Core 2 Quad (Kentsfield / Yorkfield)

Processor number Cache Processor frequency Front side bus manufacturing engineering
Q9650 12 MiB L2 3.00 GHz 1333 MHz 45 nm
Q9550 12 MiB L2 2.83 GHz 1333 MHz 45 nm
Q9450 12 MiB L2 2.66 GHz 1333 MHz 45 nm
Q9400 6 MiB L2 2.66 GHz 1333 MHz 45 nm
Q9300 6 MiB L2 2.50 GHz 1333 MHz 45 nm
Q9100 12 MiB L2 2.26 GHz 1066 MHz 45 nm
Q8300 4 MiB L2 2.5 GHz 1333 MHz 45 nm
Q8200 4 MiB L2 2.33 GHz 1333 MHz 45 nm
Q6700 8 MiB L2 2.66 GHz 1066 MHz 65 nm
Q6600 8 MiB L2 2.40 GHz 1066 MHz 65 nm
  • Implementation date: January 2007
  • Base: 775
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 36 bits
  • Addressable memory: 64 GiB

Pentium Dual-Core (Allendale)

  • Implementation date: June 5, 2007
  • Processor clock: 1.60 GHz (Pentium Dual-Core E2140), 1.80 GHz (Pentium Dual Core E2160), 2.0 GHz (Pentium Dual Core E2180), 2.2 GHz (Pentium Dual Core E2200), 2.4 GHz (Pentium Dual Core E2220), 2.93 GHz (Pentium Dual Core E6500)
  • Cache: L1 per core 32 + 32 KiB, L2 1,024 KiB
  • Bus width:
    • Data bus: 64 bit
    • Address bus: 36 bits
  • Transistors / Manufacturing Engineering: 167 million at 65 nm to 45 nm
  • Addressable memory: 64 GiB
  • Virtual memory : 64 TiB
Processor number Cache Processor frequency Front side bus manufacturing engineering
E8600 6 MiB L2 3.33 GHz 1333 MHz 45 nm
E8500 6 MiB L2 3.16 GHz 1333 MHz 45 nm
E8400 6 MiB L2 3 GHz 1333 MHz 45 nm
E8300 6 MiB L2 2.83 GHz 1333 MHz 45 nm
E8200 6 MiB L2 2.66 GHz 1333 MHz 45 nm

Core 2 Duo (Wolfdale)

  • Implementation date: Jan. 1, 2008 (E8300: April 20, 2008)
  • Processor clock: 2.66 GHz (Core 2 Duo E8200), 2.83 GHz (Core 2 Duo E8300), 3 GHz (Core 2 Duo E8400), 3.16 GHz (Core 2 Duo E8500), 3.33 GHz (Core 2 Duo E8600)
  • Socket 775
  • The first dual-core processor variant based on Penryn (45 nm).

Core i7 (Bloomfield)

  • Implementation date: November 17, 2008
  • Processor clock: 2.67 GHz (Core i7 920), 2.8 GHz (Core i7 930), 2.93 GHz (Core i7 940), 3.06 GHz (Core i7 950), 3.2 GHz (Core i7- 960), 3.2 GHz (Core i7-965 XE), 3.33 GHz (Core i7 975 XE)
  • Socket 1366
  • four physical cores
  • Cache: L1 per core 32 KiByte 8-fold associative, L2 256 KiB, L3 8 MiB
  • Die size: 107mm² x2
    • Data bus: 3x 64 bit for main memory with 1066 Mtransfers / s
    • Periphery: 2x 20 bit, QPI with 4800 to 6400 Mtransfers / s
    • Address bus: 36 bit (?)
  • Transistors / manufacturing technology: 731 million at 45 nm
  • Addressable memory: 64 GiB
  • Virtual memory : 64 TiB
  • Theoretical memory bandwidth: 25600 MByte / s for RAM, 2x 9600 to 2x 12800 MByte via QPI

2009-2013

Intel Atom (Silverthorne / Diamondville / Pine Trail / Oak Trail / Cedar Trail)

  • Implementation date: since 2008
  • Processor clock: 800 MHz to 2.13 GHz
  • Base µFCBGA
  • one or two physical cores
  • L2 cache size: 512 KiB to 1024 KiB
  • FSB clock: 100 MHz to 166 MHz
  • Manufacturing technology: 32 nm to 45 nm

Xeon (Nehalem EP / Gainestown)

  • Implementation date: March 31, 2009
  • Processor clock: 1.86 (E5502) - 3.20 GHz (W5580 / W3570)
  • Socket 1366
  • two or four physical cores
  • Cache: L1 per core 32 KiByte 8-fold associative, L2 256 KiB, L3 4/8 MiB
  • Die size: 214 mm²
    • Data bus: 64 bit
    • Address bus: 36 bits
  • Transistors / manufacturing technology: 820 million at 45 nm
  • Addressable memory: 144 GiB
  • Virtual memory : 144 TiB

Core i7 ( Nehalem )

  • Implementation date: September 8, 2009
  • Processor clock: 2.53 (i7-860s) - 3.33 GHz (i7-975 XE)
  • Socket 1156
  • Socket 1366
  • 4 physical cores

Core i5 ( Nehalem )

  • Implementation date: September 8, 2009
  • Processor clock: 2.5 (i5-750s) - 3.2 GHz (i5-4440)
  • Socket 1156
  • 4 physical cores

Core i3 ( Westmere )

  • Implementation date: January 4, 2010
  • Processor clock: 2.93 (i3-530) - 3.33 GHz (i3-560)
  • Socket 1156
  • 2 physical cores
  • 4 threads

Core i5 ( Westmere )

  • Implementation date: January 4, 2010
  • Processor clock: 3.2 (i5-650 / i5-655K) - 3.6 GHz (i5-680)
  • Socket 1156 (i7-8xx) / Socket 1366 (i7-9xx)
  • 2 physical cores

Core i7 ( Westmere )

  • Implementation date: March 16, 2010
  • Processor clock: 3.2 (i7-970) - 3.46 GHz (i7-990X)
  • Socket 1366
  • 6 physical cores

Core i5 ( Sandy Bridge )

  • Implementation date: January 9, 2011
  • Processor clock: 2.5 (i5-2400S) - 3.4 GHz (i5-2500 / i5-2550K)
  • Socket 1155
  • 4 physical cores

Core i7 ( Sandy Bridge )

  • Implementation date: January 9, 2011
  • Processor clock: 2.8 (i7-2600S) - 3.4 GHz (i7-2600 and i7-2600K) - 3.5 GHz (i7-2700K)
  • Socket 1155
  • 4 physical cores + Hyper-Threading

Core i3 ( Sandy Bridge )

  • Implementation date: February 20, 2011
  • Processor clock: 2.5 (i3-2100T) - 3.4 GHz (i3-2130)
  • Socket 1155
  • 2 physical cores + Hyper-Threading

Core i7 ( Sandy Bridge E )

Core i3 ( Ivy Bridge )

  • Implementation date: September 2011
  • Processor clock: 2.8 (i3-3220T) - 3.5 GHz (i3-3250)
  • Socket 1155
  • 2 physical cores + Hyper-Threading

Core i5 ( Ivy Bridge )

  • Implementation date: April 2012
  • Processor clock: 3.2 (i5-3330 and i5-3340) - 3.8 GHz (i5-3570)
  • Socket 1155
  • 4 physical cores (i5-3470T with 2 cores and Hyper-Threading )

Core i7 ( Ivy Bridge )

  • Implementation date: April 2012
  • Processor clock: 3.7 (i7-3770T) - 3.9 GHz (i7-3770K)
  • Socket 1155
  • 4 physical cores + Hyper-Threading

Core i3 (Haswell)

Core i5 (Haswell)

  • Implementation date : Q2 2013
  • Processor clock: 3.0 GHz (i5-4430) - 3.9 GHz (i5-4690 and i5-4690K)
  • Socket 1150
  • 4 physical cores (i5-4570T with 2 cores and Hyper-Threading )

Core i7 (Haswell)

  • Implementation date : Q2 2013
  • Processor clock: 2.7 GHz (i7-4790T) - 4.4 GHz (i7-4790K)
  • Socket 1150
  • 4 physical cores + Hyper-Threading

Others

  • The iAPX 432 , introduced in 1981, was extremely complex and very slow, so it became a big flop.
  • The i860 series was an attempt to produce RISC processors for scientific calculations, such as in the massively parallel high-performance computer Intel Paragon, but mainly used in the embedded area and in HP laser printers.
  • Intel produced many embedded processors, e.g. B. the i960 series.
  • Intel carries various network processors ( Intel IXP series).
  • Intel carries various I / O processors ( Intel IOP series).
  • Intel Polaris : a processor with 80 cores that is clocked at up to 5.76 GHz and has a computing power of 1.81 teraflops and a power loss of up to 265 watts. Intel presented this research CPU in February 2007.

Itanium 2 series

  • McKinley (first Itanium II processor)
    • Implementation date: July 8, 2002
    • Processor clock: 900 MHz, 1 GHz
    • Cache: 1.5 [MiB], 3.0 [MiB]
    • Bus width: 128 bits
    • Transistors / manufacturing technology: 221 Mill (plus ext. L3 cache) / 180 nm
    • Addressable memory: 18 TiB
    • The McKinley core is the first Itanium II to address some of the major shortcomings of the old Itanium (Merced core). The high latency times of the L1 and L2 caches have been reduced and the L3 cache has also been integrated directly on the die. The front side bus was widened from 64 to 128 bits and accelerated from 266 to 400 MHz. The execution speed of the x86 emulation has also been increased.
  • Madison
    • Implementation date: June 30, 2003
    • Processor clock: 1.3-1.6 GHz;
    • Cache: 1.5 [MiB] - 6.0 [MiB]
    • Bus width: 128 bits
    • Transistors / manufacturing technology: 221 Mill / 130 nm
    • Addressable memory: 18 TiB
    • The Madison Core integrates further performance improvements. Processors with 1.5 GHz with 6 MiB cache, 1.4 GHz with 4 MiB and 1.3 GHz with 3 MiB were new to the portfolio. The 1.5 GHz version achieved the highest SpecFP and SpecInt values ​​of a series-produced single processor.
  • Deerfield (low power version)
    • Implementation date: September 8, 2003
    • Processor clock: 1.0 GHz;
    • Cache: 1.5 [MiB]
    • Bus width: 128 bits
    • Transistors / production technology: 221 Mill (plus external L3 cache) / 0.13 µm
    • Addressable memory: 18 TiB
    • The Deerfield Core is the first energy-saving version (62 watts) of the Itanium II and is recommended for systems with high CPU density (clusters).
  • Hondo (first version with dual core and L4 cache)
    • Implementation date: 1Q 2004
    • Processor clock: 1.1 GHz dual core
    • Cache: 3.0 [MiB] L3, max. 32 MiB L4
    • Bus width: 128 bits
    • Transistors / manufacturing technology: 410 million (plus external L4 cache) / 0.13 µm
    • Addressable memory: 18 TiB
    • The Hondo is both the first Itanium II version with L4 cache and the first dual-core version, it was marketed exclusively by HP.
  • Fanwood (version optimized for DP operation)
    • Implementation date: November 8, 2004
    • Processor clock: 1.3-1.6 GHz
    • Cache: 3.0 [MiB]
    • Bus width: 128 bits
    • Transistors / manufacturing technology: 210 million / 0.13 µm
    • Addressable memory: 18 TiB
    • The Fanwood is a simplified version of the Madison 9M, it is optimized for dual processor (DP) operation and offers an FSB of 533 MHz for the first time; a low-voltage version is also available.
  • Madison 9M
    • Implementation date: November 8, 2004
    • Processor clock: 1.6-1.67 GHz;
    • Cache: 6.0 [MiB] - 9.0 [MiB]
    • Bus width: 128 bits
    • Transistors / manufacturing technology: 590 million with 9 MiB cache, 410 million with 6 MiB cache / 130 nm
    • Addressable memory: 18 TiB
    • The Madison 9 M integrates further performance improvements and for the first time offers an FSB of 667 MHz. A version of the Madison 9M called Fanwood is available for the low-end range.
  • Montecito (first Itanium dual-core with 24 MiB cache, 90 nm)
    • Itanium 9000 series
    • Implementation date: July 18, 2006
    • Processor clock: 1.4-1.6 GHz; Single-core, dual-core
    • Cache: 24.0 [MiB] (12 MiB per core)
    • Bus width: 128 bits
    • Transistors / manufacturing technology: 1.77 billion / 90 nm
    • Addressable memory: 64 GiB
    • The Montecito is the first Intel Itanium II with two cores per die and with 24 MiB cache, it is manufactured in the 90 nm process. Hardware-based virtualization, which allows multiple operating systems to be used equally on one system, and multithreading are new. For the first time there is no hardware-based IA-32 (x86, 32-bit) support.
  • Montvale
    • Itanium 9100 series
    • Implementation date: October 31, 2007
    • Processor clock: 1.66 GHz; Single-core, dual-core
    • Cache: 8–24.0 [MiB] (4–12 MiB per core)
    • Bus width: 128 bits
    • Transistors / manufacturing technology: 1.77 billion / 90 nm
    • Addressable memory: 18 TiB
    • The Montvale is an optimized Montecito and brings few innovations for server operation (core-level lockstep, demand-based switching).
  • Tukwila (first Itanium quad-core)
    • Itanium 9300 series
    • Implementation date: February 10, 2010
    • Processor clock: 1.33-1.86 GHz; Dual-core, quad-core
    • Cache: 10–30.0 [MiB] (4–6 MiB L3 per core)
    • Bus width: QPI ( DDR3 , max.throughput per core 34 GB / s)
    • Transistors / manufacturing technology: 2.046 billion / 65 nm
    • Addressable memory: 1,024 TiB
    • Most important innovations: QPI for DDR3 Ram, Turbo-Boost (temporary frequency increase of individual cores, if not all cores are fully utilized), various extensions for "Mission-Critical Computing" (virtualization, hot-plug, etc.). First marketable processor with more than 2 billion transistors.
  • Poulson
    • Itanium 9500 series
    • Release DATE: November 8, 2012
    • Processor clock: 1.73 GHz to 2.53 GHz; Quad core; Octo-core
  • Kittson
    • Itanium 9700 series
    • Release DATE: May 11, 2017
    • Processor clock: 1.73 GHz to 2.66 GHz; Quad core; Octo-core

Rock Creek

  • The Rock Creek is an experimental multi-core processor that was introduced by Intel in December 2009.

Terms

  • x86 - stands for all processors compatible with the 8086, including CPUs from Intel competitors
  • XT - short for Extended Technology, belonging to the 8086
  • AT - short for Advanced Technology, part of the 80286, XT successor
  • 286 - short for the 80286
  • 386 - short for the 80386 / i386
  • 486 - short for the 80486 / i486
  • iAPX - Marketing term for Intel processors introduced in the late 1980s for trademark protection reasons
  • iA-32 - Designation for the 32-bit architecture introduced with the 80386 , which extends the 16-bit instruction set of its predecessors (however, this designation was created late to differentiate it from iA-64)
  • iA-64 - new 64-bit architecture , fundamentally different from the iA-32, developed by Intel and HP , used in the Itanium
  • x64 - the 64-bit extension of the x86 architecture implemented by AMD64 and Intel 64
  • Centrino - Marketing initiative from Intel, the use of the label Centrino requires a Pentium M processor, an Intel chipset and a WLAN interface from Intel
  • Centrino Duo - Marketing initiative from Intel, the use of the label Centrino Duo requires a Yonah or Merom processor, an Intel chipset and a WLAN interface from Intel.
  • Viiv - (spoken like English wife: wife) - Marketing initiative by Intel for media center PCs

See also

Web links

Individual evidence

  1. ↑ http://download.intel.com/products/processor/itanium/318691.pdf
Intel processors
Pre- x86 processors
Desktop

4004  • 4040  • 8008  • 8080  • 8085

x86 up to the 4th generation
Desktop

8086  • 8088  • 80186  • 80188  • 80286  • 80386 (i386)  • 80486 (i486)  • Overdrive versions

Pentium series
Desktop

Pentium (MMX)  • Pentium II  • Pentium III  • Pentium 4  • Pentium 4 XE  • Pentium D  • Pentium XE  • Pentium Dual-Core  • Overdrive versions

Mobile

Mobile Pentium 4  • Pentium M  • Pentium Dual-Core

server

Pentium Pro

Celeron series
Desktop

Celeron (P6)  • Celeron (NetBurst)  • Celeron D  • Celeron (Core)  • Celeron Dual-Core

Mobile

Mobile Celeron  • Celeron M

Core series
Desktop

Core ( Core Solo , Core Duo ) • Core 2  • Core i  • Core M

Xeon series
ii server

Xeon (P6)  • Xeon (NetBurst)  • Xeon (Core)  • Xeon (Nehalem)  • Xeon (Sandy Bridge)  • Xeon (Ivy Bridge)  • Xeon (Haswell)  • Xeon (Broadwell)  • Xeon (Skylake)  • Xeon (Kaby Lake)  • Xeon (Coffee Lake)  • Xeon (Cascade Lake)

Atom series
Desktop

atom

x86-compatible SoCs
Desktop

Quark  • Edison

Non-x86 processors
Desktop

iAPX 432  • i860  • i960  • Itanium  • Itanium 2  • XScale

Further lists:  Celeron  •  Pentium  •  Core 2  •  Core i