Intel Celeron (NetBurst)

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Intel Celeron
Celeron Logo alt.svg
Celeron emblem
Production: 2002 to 2004
Producer: Intel
Processor clock: 1.7 GHz to 2.8 GHz
FSB cycle: 100 MHz
L2 cache size: 128 KiB
Instruction set : x86
Microarchitecture : NetBurst
Base: Socket 478
Names of the processor cores:
  • Willamette
  • Northwood
Old Celeron emblem

With the Intel Celeron processor based on the NetBurst architecture, Intel continued in 2002 the path begun with the Intel Celeron based on the P6 architecture of offering processors under its own brand name for the low-price segment. As part of the equipment of all Intel microprocessors with a model number was this series by the Intel Celeron D replaced.

Technical

The Intel Celerons have a smaller L2 cache , a lower clocked front side bus and are mostly only available with lower clock frequencies than the corresponding Intel Pentium 4s . This means that the performance of these CPUs is very limited, but the lower production costs reduce the sales price.

Some Intel Celeron based on the NetBurst architecture were not manufactured separately. In the case of slightly defective Intel Pentium 4 processors - usually those with a partially defective cache - the defective or "superfluous" cache areas were simply deactivated, and the CPUs came onto the market with a lower specified clock rate than Intel Celeron . Of course, processors with errors in essential CPU functional units did not make it onto the market.

Model data socket 478

Willamette-128

Intel Celeron 1.7 GHz (Willamette-128)
  • L1 cache: 8  KiB (data) + 12,000 µOps (instructions)
  • L2 cache: 128 KiB with processor clock
  • MMX , SSE , SSE2
  • Socket 478 , AGTL + with 100 MHz (quadpumped, FSB 400)
  • Operating voltage ( VCore ): 1.75 V.
  • Power dissipation ( TDP ):
  • Release DATE: May 15, 2002
  • Manufacturing technology: 180 nm
  • The size: 217 mm² with 42 million transistors
  • Clock rates:
    • 1.7 GHz
    • 1.8 GHz

Northwood-128

Celeron with 2 GHz (Northwood-128)
  • L1 cache: 8  KiB (data) + 12,000 µOps (instructions)
  • L2 cache: 128 KiB with processor clock
  • MMX , SSE , SSE2
  • Socket 478 , AGTL + with 100 MHz (quadpumped, FSB 400)
  • Operating voltage ( VCore ): 1.475-1.525 V.
  • Power dissipation ( TDP ): 59.8 W.
  • Release DATE: September 18, 2002
  • Manufacturing technology: 130 nm
  • The size: 131 mm² with 55 million transistors
  • Clock rates:
    • 2.0 GHz
    • 2.1 GHz
    • 2.2 GHz
    • 2.3 GHz
    • 2.4 GHz
    • 2.5 GHz
    • 2.6 GHz
    • 2.7 GHz
    • 2.8 GHz