Front side bus

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Scheme of a chipset (FSB green)

In computer technology, the front side bus ( FSB ) is an interface between the main processor (CPU) and the northbridge .

More modern processors with integrated memory controllers (from AMD Athlon 64 and Intel Core i series ) are no longer connected to the Northbridge via a classic FSB, but via a HyperTransport or QPI connection.


On the Northbridge are usually the main memory ( RAM ) and the AGP - slot or PCI Express slot the graphics card connected. The southbridge , which is connected to the northbridge via a bus , controls the I / O interfaces such as hard disk , USB or network interfaces. The FSB specifies the clock rate for all the components addressed, which can be changed using dividers and multipliers (example: processor clock rate = FSB × CPU multiplier).

The power of the front side bus is usually given as the clock frequency of the bus, in the case of DDR or QDR buses the corresponding multiple. The data width or maximum transmission rate, on the other hand, is usually not specified as a characteristic feature.

FSB variants

In systems based on the Pentium 4 , Pentium M or Intel Core based working front side bus in the QDR method ( Q uadruple D ata R ate  = four times the data rate), and transmits four data packets per clock signal. This process was called quadpumped by Intel's marketing department in order to be able to convey this technical characteristic better and more sonorous. However, this also resulted in incorrect information about the clock frequency of the FSB: The FSB of these processors runs at a clock frequency of 100 to 400 MHz ("FSB 400" to "FSB 1600"), but is always happy - albeit incorrectly - as 400 - up to 1600- "MHz" -FSB denotes what the word creation "Marketing-MHz" has produced.

A similar process in FSB sets AMD when base A or IBM in the PowerPC G5 model: where the FSB runs in the DDR process ( D ouble D ata R ate  = double data rate), and transmits two data packets per clock signal. Here too, the term 200 to 400 “MHz” FSB is often incorrectly referred to, although it is actually a 100 to 200 MHz FSB (“FSB 200” to “FSB 400”).

In older computer systems such as base 7 , socket 370 or over the FSB in running SDR method ( S ingle D ata R ate = single data rate), and transmits a data packet per clock signal. A specification like "FSB 100" always designates the clock frequency of the FSB in MHz (here 100 MHz).

Usual clock frequencies and names
Clock frequency designation
DDR-FSB ("Doublepumped")
100 MHz FSB 0200
133 MHz FSB 0266
166 MHz FSB 0333
200 MHz FSB 0400
QDR-FSB ("Quadpumped")
100 MHz FSB 0400
133 MHz FSB 0533
166 MHz FSB 0667
200 MHz FSB 0800
266 MHz FSB 1066
333 MHz FSB 1333
400 MHz FSB 1600

Data rate using the example of the Series 4 chipset from Intel

The FSB of the Intel 4 series chipset family for Intel Core 2 processors and LGA775 socket consists of 32 address lines, 64 data lines and control and clock lines. The address lines are operated in the DDR method (two transfers per cycle), with 32 address lines, a 64-bit address can be transmitted in each cycle. The data lines run in the QDR process (four transfers per cycle). This means that 4 × 64 = 256 bits or 256/8 = 32 bytes can be transmitted per cycle. As the smallest memory unit, the processors used with the chipset transport a cache line (64 bytes) to and from the RAM, which requires two clocks. The chipset supports an FSB clock of 200, 266 or 333 MHz, multiplied by 32 bytes results in a data rate of 6.4 or 8.5 or a maximum of 10.6 gigabytes / s on the data bus.

See also

Individual evidence

  1. Intel® 4 Series Chipset Family Datasheet, March 2010, page 525f