Double data rate

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In computer technology, double data rate (DDR, also: doublepumped ) refers to a process with which data can be transmitted on a data bus at double the data rate .

Similar methods are Quadruple Data Rate (QDR) with four times the data rate and Octal Data Rate (ODR) with eight times the data rate.

Technology in the GDR

The data bits are transmitted on the rising and falling edge of the clock signal , instead of only on the rising edge as in the conventional single data rate method. So that the frequency of access to the memory cells does not have to be doubled, the so-called ' prefetch ' technique is used: with one access, twice as much data is fetched from the memory field as can be sent to the outside at once. Half of the data is output with the rising clock edge, while the other half is buffered and only output with the falling edge. So that this leads to an acceleration, the number of connected data requested (= 'Burst-Length') must always be equal to or greater than twice the bus width. Since this is not always the case, the data throughput with DDR-SDRAM is not exactly twice as high compared to classic (SDR) SDRAM with the same clock frequency. Another reason for this is that, in contrast to the data signals, address and control signals are only provided with one clock edge.


The technology is used, for example, to connect processors ( Front Side Bus , QPI , HyperTransport ), main memory ( DDR-SDRAM ), mass storage ( Ultra-160 / Ultra-3 SCSI ) and graphics cards ( PCIe ).


When specifying the clock frequencies of double data rate connections, the clock frequency of the bus is often confused with the data rate. B. a processor bus with 100 MHz clock frequency and double data rate is referred to as a "200 MHz bus". This is sometimes referred to as the effective clock .

A designation beginning with PC and three digits after that indicates the bus rate in MHz (e.g. PC-133 or PC133 = 133 MHz). Four digits, on the other hand, denote the data transfer rate in Mbytes / s, so the PC-2700 indicates a DDR-SDRAM memory module intended for 166 MHz. Calculation: 166 MHz * 2 (since DDR) * 64 bit (bus width) = 21248 Mbit / s / 8 bit / byte = 2656 Mbyte / s, rounded up to 2700 Mbyte / s. The PC information is therefore not limited to DDR technology and only makes sense in connection with the specification of the bus and technology designation (this then clearly defines the bus width and factor).

Further developments: DDR2 and DDR3

DDR2 and DDR3 are further developments of this concept, especially for PC main memories, which work with quadruple or eightfold prefetch instead of double prefetch in order to enable a higher clock rate of the I / O buffer . With DDR2, the actual memory cells are only operated at half the rate of the I / O buffer . The quadruple prefetch, which is often referred to here from a marketing point of view, is created on the one hand via the DDR process (× 2) and on the other via this clock doubling (× 2) - a total of quadruple prefetch. With DDR3 this is increased to the extent that there is a four-fold difference between the clock of the I / O buffers and the clock of the actual memory cells - together with the DDR process, an eight-fold prefetch. Although the memory cells make up the significantly larger part of the memory chip (90%), the clock rate of the I / O buffers is considered "official" when specifying the clock of DDR2 / DDR3 memories .

Side developments: GDDR2 and GDDR3

GDDR2 and GDDR3 are memory types that are only installed on graphics cards. Contrary to what the name suggests, GDDR2 is based on DDR-SDRAM and GDDR3 is based on DDR2-SDRAM. This has to do with the fact that GDDR2 and GDDR3 are not official specifications, but only represent the marketing names of the major graphics chip developers.

Related developments: QDR and QDR II

Quad Data Rate -RAM describes a component that combines the advantages of DDR-SDRAM and dual-port RAM . It has separate read and write ports so that read and write can be carried out independently of one another without collision. However, the data share a common address line. This means that the QDR-SRAM can transmit data on both ports at the same time with a rising and falling edge, which results in a four-fold increase in the data rate. There are two types of QDR SRAMs, the 2-word burst variant and the 4-word burst variant. This means that with a read or write access, 2 or 4 words are read or written. QDR finds z. B. Use with the system bus of the Pentium 4 , ODR with the AGP bus (AGP-8X) and with XDR-DRAM .

QDR II -RAM is the improved variant of the QDR-RAM with returned clock outputs, so-called echo clocks, which are used for synchronization. This widens the window of valid data at the same frequency by up to 35%. Compared to QDR-SRAMs, the latency is half a clock longer, but overall higher data rates can be used, so that throughput increases.

Individual evidence

  1. Hartmut Ernst, Jochen Schmidt, Gerd Beneken: Basic course in computer science . 5th edition. Springer Fachmedien , Wiesbaden 2015, ISBN 978-3-658-01628-9 , pp. 247 .