Intel Xeon (P6)
Intel Xeon | |
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![]() Xeon P6 series logo |
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Producer: | Intel |
Processor clock: | 400 MHz to 1000 MHz |
FSB cycle: | 100 MHz to 133 MHz |
L2 cache size: | 256 KiB to 2 MiB |
Instruction set : | x86 |
Microarchitecture : | Intel P6 |
Base: | |
Names of the processor cores:
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The Intel Xeon series based on the Intel P6 architecture is a family of 32-bit microprocessors for servers and workstations . They were the first processors that Intel developed specifically for this market segment. With them, Intel introduced the brand name Intel Xeon . The dimensions of the SEC (Single Edge Contact) cartridge of the Pentium II / III Xeon, which is large compared to the non-Xeon models, are: 123 × 153 × 19 mm (height × width × depth).
Model data
Drake
- L1 cache: 16 + 16 KiB (data + instructions)
- L2 cache: 512, 1024 or 2048 KiB (on package)
- MMX
- Slot 2 , GTL + with 100 MHz (SDR)
- Power consumption ( TDP ): up to 46.7 W.
- Release DATE: June 29, 1998
- Manufacturing technology: 250 nm
- Clock rates:
- 512 KiB L2 cache: 400 and 450 MHz
- 1024 KiB L2 cache: 400 and 450 MHz
- 2048 KiB L2 cache: 450 MHz
Tanner
- L1 cache: 16 + 16 KiB (data + instructions)
- L2 cache: 512, 1024 or 2048 KiB (on package)
- MMX , SSE
- Slot 2 , GTL + with 100 MHz (SDR)
- Power consumption ( TDP ): up to 39.5 W.
- Release DATE: March 17, 1999
- Manufacturing technology: 250 nm
- Clock rates:
- 512 KiB L2 cache: 500 and 550 MHz
- 1024 KiB L2 cache: 500 and 550 MHz
- 2048 KiB L2 cache: 500 and 550 MHz
Cascades
- L1 cache: 16 + 16 KiB (data + instructions)
- L2 cache: 256 KiB (on-die with full processor clock), 1024 or 2048 KiB (on-package)
- MMX , SSE
- Slot 2 (FSB 100) and Socket 495 (FSB 133), GTL + with 100 or 133 MHz (SDR)
- Power consumption ( TDP ): up to 44 W.
- Release DATE: October 25, 1999
- Manufacturing technology: 180 nm
- Clock rates:
- 256 KiB L2 cache:
- FSB 100: 600 MHz
- FSB 133: 667, 733, 800, 866, 933 and 1000 MHz
- 1024 KiB L2 cache (FSB 100): 700 MHz
- 2048 KiB L2 cache (FSB 100): 700 and 900 MHz
- 256 KiB L2 cache: