Socket 775

from Wikipedia, the free encyclopedia
Socket 775
Socket 775
introduction 2004
design type LGA
contacts 775
Bus protocol AGTL +
Bus cycle 133 MHz ( quad-pumped ), FSB533
200 MHz ( quad-pumped ), FSB800
266 MHz ( quad-pumped ), FSB1066
333 MHz ( quad-pumped ), FSB1333
400 MHz ( quad-pumped ), FSB1600
Processors Intel Pentium 4
Intel Pentium 4 EE
Intel Pentium D
Intel Pentium EE
Intel Celeron
Intel Core 2 Duo
Intel Core 2 Quad
Intel Core 2 EE
Intel Xeon

The Socket 775 (also: LGA775 ( land grid array ) and Socket T ) is a processor socket for Intel - processors of Pentium 4 - Celeron - Core 2 -, Celeron Dual-Core and Pentium dual core family.

Socket 775 replaced Socket 478 for the Pentium 4 in order to enable higher clock frequencies and a faster front side bus . With the Socket 775 Intel turns of processors in Pin Grid Array - Package from. Processors in LGA housings have contact surfaces instead of contact pins. As the clock frequency of the front side bus increased, the pins caused electromagnetic interference (antenna effect), which can interfere with surrounding electronic components.

Parallel to the Socket 775, Intel introduced some new technologies such as DDR2-SDRAM - RAM and PCI-Express . Mainboards with LGA775 chipset could initially be equipped with DDR-SDRAM as well as DDR2-SDRAM of the types PC2-3200, PC2-4200 and PC2-5300-DIMMs, since mid-2006 PC2-6400-DIMMs have also been supported. DDR3 memory is also supported. This is possible because the memory controller is not located in the CPU but in the chipset.

The development name Socket T is derived from the Pentium 4 processor with Tejas core originally planned for this socket .

The number 775 in the name "Socket 775" is based on the number of contacts. The Socket 775 was first introduced to the public by Intel in June 2004 in response to AMD's presentation of the Socket 939 .

Web links

Commons : Socket 775  - Collection of pictures, videos and audio files

Individual evidence

  1. Heise Newsticker: Intel's Pentium 4 processors soon with a larger L2 cache from Sept. 2, 2004