DDR SDRAM

Two DDR-SDRAM modules: at the top 512 MiB equipped with a heatspreader on both sides , at the bottom 256 MiB equipped on one side

Different desktop DDR modules: DDR1 has fewer and larger contacts than its successors: 1.27 mm / pin. DDR2 and DDR3: 1.00 mm / pin. DDR4: 0.85mm / pin. From DDR3 the four side recesses are angular. SDR-SDRAM (not in the picture) has two notches in the contact strip.

DDR-SDRAM ( English Double Data Rate Synchronous Dynamic Random Access Memory ; often just: DDR-RAM ) is a type of random access memory (RAM), i.e. a special semiconductor memory that is currently (as of 2019) in five variants gives. These are mainly used for memory modules of the DIMM and SO-DIMM standards and as main memory in PCs and laptops . There is a separate specification for mobile devices ( Low Power SDRAM ), as well as for graphics memory (see GDDR ).

history

In mid-1999 put the computer industry to the development of SDRAM in the form of GDR -Speichertechnik because of Intel Compatible Direct Rambus DRAM technology (RDRAM) by an error in the i820 chipset got problems and by the Pentium III - FSB her Could not play to performance despite high prices.

The first memory chips and mainboards with support for DDR SDRAM came on the market at the end of 1999. However, it was not until the beginning of 2002 that they were able to establish themselves on the European end consumer market.

Overview

DDR SDRAM standard	Clock rate (MHz)		pre- fetch	Transfer rate	tension	Pins			Remarks
	Storage	I / O		(MT / s)	(V)	DIMM	SO-	Micro
GDR0	100-200	0100- 0200	2n	0200- 0400	2.5 / 2.6	184	200	172
DDR2	100-266	0200- 0533	4n	0400-1066	1.8	240	200	214
DDR3	100-266	0400-1066	8n	0800-2133	1.5 / 1.35	240	204	214
DDR4	200-400	0800-1600	8n	1600-3200	1.05 / 1.2	288	260	-
DDR5	200-525	1600-4200	16n	3200-8400	1.1	?	?	-	two 32-bit channels, dual parity °), On-Die-ECC °°)

°) Increase from 8 to 16 bit parity per 64 bit memory line
°°) Even non-ECC RAM has parity bits that the memory uses for internal memory correction independently of the CPU.

Working method

PC-3200 module with DDR-400 chips

... and the back

DDR SDRAM

While "normal" SDRAM modules offer a data transfer rate of 1.06  GB / s at a clock rate of 133 MHz , modules with DDR-SDRAM (133 MHz) work almost at twice the data rate. This is made possible by a relatively simple trick: a data bit is transmitted on both the rising and falling edge of the clock signal, instead of only the rising edge , as was previously the case.

So that the double data rate method leads to an acceleration, the number of consecutively requested data (= "burst length") must always be equal to or greater than double the bus width. Since this cannot always be the case, DDR-SDRAM is not exactly twice as fast compared to simple SDRAM with the same clock rate. Another reason is that, in contrast to the data signals, address and control signals are only given with one clock edge.

DDR-SDRAM memory modules (DIMM) have 184 contacts / pins (DDR2-SDRAM DIMM / DDR3-SDRAM DIMM: 240, SDRAM DIMM: 168 contacts). The operating voltage is usually 2.5 V, for DDR-400 2.6 V.

Specifications

chip	module	Storage cycle	I / O cycle	Effective tact	Transfer rate
					per 64-bit module
DDR-200	PC-1600	100 MHz	100 MHz	200 MHz	1.6 GB / s
DDR-266	PC-2100	133 MHz	133 MHz	266 MHz	2.1 GB / s
DDR 333	PC-2700	166 MHz	166 MHz	333 MHz	2.7 GB / s
DDR-400	PC-3200	200 MHz	200 MHz	400 MHz	3.2 GB / s

² : Speed ​​of connection to the memory controller of the CPU or mainboard

³ : Effective clock rate compared to SDR-SDRAM (theoretical)

PC-XXXX: The XXXX is calculated as (2 × memory cycle × bus width) / 8 (bus width = 64 bit) and corresponds to the data rate in MB / s.

DDR-200 to DDR-400 and the PC-1600 to PC-3200 memory modules built with them are standardized by JEDEC as JESD79. All modules that differ from this are based on the designation of the standards, but every manufacturer uses its own specifications for the electrical properties - these modules are often offered as "overclocking memories" - and often works with excessive overvoltage.

The memory modules with ECC ( Error Checking and Correction ) or registered modules with signal buffers , which are often used in servers , provide a security gain. However, this only applies if these memory modules are explicitly supported; ECC modules often do not work at all in normal desktop motherboards. Such memory modules are available in all standardized clock frequencies and can be identified by the additional designation R , ECC or R ECC , for example PC-1600R, PC-2100 ECC or PC-2700R ECC.

DDR2 SDRAM

512-MiB-PC2-4200 memory module: The chips are housed in a BGA housing. The designation 32M8 CEC means 32 Mibit × 8 = 256 Mibit or 32 MiB storage capacity per chip.

DDR2-SDRAM is a further development of the concept of DDR-SDRAM, in which a quadruple prefetch is used instead of a double prefetch .

The modules for desktop computers have 240 instead of 184 contacts / pins and are mechanically and electrically incompatible with DDR modules. A differently arranged notch prevents mix-ups.

The housings of the memory chips are made using FBGA (Fine Ball Grid Array) technology and are smaller (126 mm² instead of the previous 261 mm²) than standard DDR RAM in the TSOP (Thin Small Outline Package) housing.

With DDR2-SDRAM, the I / O buffer is clocked at twice the frequency of the memory chips. As with the older DDR standard, valid data is obtained with a rising and falling edge of the clock signal. With DDR-SDRAM (at least) two consecutive addresses are read with a read command, with DDR2-SDRAM four, due to the prefetch method of the respective standard. 256 bits are read per read access from a 128-bit DDR module, 512 from a comparable DDR2 module. The absolute amount of data remains identical with the same I / O cycle of 200 MHz, for example, since the DDR2 module has two cycles rather than one needed to transfer the data. DDR2 only supports two possible burst lengths (number of data words that can be read or written with a single command), namely four (due to quadruple prefetch) or eight, while DDR supports two, four or eight.

To reduce the electrical power consumption, the signal and supply voltage of DDR2-SDRAM was reduced to 1.8 V (with DDR-SDRAM it is 2.5 V). In addition, the reduced voltage causes less heat generation, which in turn can lead to higher clock rates being achieved.

DDR2-SDRAM chips work with "On- Die Termination" (ODT). The memory bus no longer has to be terminated on the module circuit board (or the board). The termination function was integrated directly into the chips, which saves space and costs. With ODT, the memory controller sends a signal on the bus that causes all inactive memory chips to switch to termination. This means that only the active signal is on the data line, interference is as good as impossible.

compatibility

DDR2 modules can in principle be used in any motherboard with DDR2 slots regardless of their speed specification. The memory controller ensures that memory modules that are slower than the motherboard are operated at a maximum of the clock rate for which they are designed.

DDR2 modules with different clock rates can also be combined as required. In most cases, however, the entire memory only works at the speed of the slowest module.

However, since the JEDEC specifications are imprecise, compatibility problems between certain mainboards and certain memory modules can arise. Often these problems can be solved by a BIOS update. Only with memory that is on the so-called QVL (Qualified Vendor List) of the mainboard can it be assumed that it will definitely work in this mainboard.

Specifications

chip	module	Storage cycle	I / O cycle	Effective tact	Transfer rate
					per 64-bit module
DDR2-4000	PC2-3200	100 MHz	200 MHz	400 MHz	3.2 GB / s
DDR2-5330	PC2-4200	133 MHz	266 MHz	533 MHz	4.2 GB / s
DDR2-6670	PC2-5300	166 MHz	333 MHz	667 MHz	5.3 GB / s
DDR2-8000	PC2-6400	200 MHz	400 MHz	800 MHz	6.4 GB / s
DDR2-1066	PC2-8500	266 MHz	533 MHz	1066 MHz	8.5 GB / s

² : Speed ​​of connection to the memory controller of the CPU or mainboard

³ : Effective clock rate compared to SDR-SDRAM (theoretical)

PC2-XY00: The XY00 is calculated using (4 × memory clock [in MHz] × bus width [in bits]) / 8 (bus width = 64 bits) and corresponds to the data rate in MB / s.

DDR2-400 to DDR2-1066 and the PC2-3200- to PC2-8500 memory modules built with them are standardized by JEDEC . All modules that differ from this are based on the designation of the standards, but each manufacturer sets its own specifications for the electrical properties - the modules often offered as "overclocking memory" - and often works with excessive overvoltage. As with DDR-SDRAM, there are also registered modules (PC2-XY00 R ) and ECC modules (PC2-XY00 E ) as well as FBDIMM modules in addition to the unregistered modules (often referred to as PC2-XY00 U ) . Module (PC2-XY00 F ).

DDR3 SDRAM

DDR3 module: The notch is much closer to the edge than DDR2 modules.

DDR3 modules in low-voltage design

PC3-10600 DDR3- SO-DIMM (204 pins)

DDR3-SDRAM is a further development of the concept of DDR2-SDRAM, in which an eight- fold prefetch is used instead of a four-fold prefetch .

The chips with a capacity of at least 512 Mebi bits process data at 8500 megabytes per second and are therefore significantly faster than DDR-400 or DDR2-800 SDRAM. However, the CAS latency is higher. DDR3-SDRAM is operated with 1.5 V instead of 1.8 V and is therefore more suitable for mobile use where long battery life is important. Low-voltage versions (DDR3L) can be operated with 1.35 V on suitable motherboards. Ultra-low-voltage versions (DDR3U) are intended for operation with 1.25 V.

DDR3 SDRAM memory modules (DIMM) have 240 contacts / pins. Despite having the same number of pins, they are not compatible with DDR2-SDRAM and have different notches. SODIMM modules for notebooks have 204 contacts compared to 200 contacts as DDR2 variant and DDR1 variant.

In the area of graphics memory , GDDR 3 memories have been used for a long time . However, this is based on DDR2 memory chips, only the voltage was initially lowered (voltage VDD = 1.5 V instead of 2.5 V; VDDQ = 1.5 V instead of 1.8 V). The name GDDR3 has no official specifications, but was chosen for marketing reasons (to differentiate itself from the less successful GDDR2). GDDR4 and GDDR5 are based on DDR3 technologies, but are in some cases considerably modified for use as graphics memory.

Specifications

chip	module	Storage cycle	I / O cycle	Effective tact	Transfer rate
					per 64-bit module
DDR3-8000	PC3-64000	100 MHz	400 MHz	800 MHz	6.4 GB / s
DDR3-1066	PC3-85000	133 MHz	533 MHz	1066 MHz	8.5 GB / s
DDR3-1333	PC3-10600	166 MHz	666 MHz	1333 MHz	10.6 GB / s
DDR3-1600	PC3-12800	200 MHz	800 MHz	1600 MHz	12.8 GB / s
DDR3-1866	PC3-14900	233 MHz	933 MHz	1866 MHz	14.9 GB / s
DDR3-2133	PC3-17000	266 MHz	1066 MHz	2133 MHz	17.0 GB / s

²: Speed ​​of connection to the memory controller of the CPU or mainboard

³: Effective clock rate compared to SDR-SDRAM (theoretical)

PC3-XXXX: The XXXX is calculated as (8 × memory clock [in MHz] × bus width of a module) / 8 and corresponds to the data rate in MB / s. The data bus width of a module is always 64 bits (= 8 bytes). In addition, 8 × 4 GB can be addressed per module (address bus only requires 32 bits).

The specifications from DDR3-800 to DDR3-2133 and the PC3-6400- to PC3-17000 memory modules built with them are described by the standardization organization JEDEC . All modules that differ from this are based on the designation of the standards, but each manufacturer sets its own specifications for the electrical properties - the modules often offered as "overclocking memory" - and often works with excessive overvoltage. As with DDR1-SDRAM, there are also ECC and Registered modules for DDR3-SDRAM , but these are currently (May 2011) only standardized up to and including PC3-12800. Similar to earlier standards, these are provided with the additional identifier R , ECC or R ECC . An identifier PC3L- designates low-voltage memory modules, PC3U- stands for ultra-low-voltage memory modules. Similarly, the names DDR3L or DDR3U for corresponding memory chips.

DDR4 SDRAM

DDR4 memory module

DDR4-2666 4x8 GB with heat sink

A DDR4-SDRAM has 288 contacts, the notebook counterpart SO-DIMM has 260 contacts. As with DDR3-SDRAM, the memory is operated with 8-fold prefetch . So there is no duplication, as was the case with the previous DDR-SDRAM generations. Instead, the modules can be operated with higher clock rates. The new memory modules are to be manufactured using the 30 nanometer process.

In May 2012, Micron delivered the first test copies of DDR4 SDRAMs and they were launched in mid-2014. Originally, it was supposed to achieve at least 50 percent market share by 2015; later estimates assumed that this target could be achieved in 2016 at the earliest. According to current projections (04/2017), the breakthrough will come in 2017. This means that the DDR3 standard introduced in 2007 was largely replaced only after about ten years.

Specifications

chip	module	Storage cycle	I / O cycle	Effective tact	Transfer rate
					per 64-bit module
DDR4-1600	PC4-12800	200 MHz	800 MHz	1600 MHz	12.8 GB / s
DDR4-1866	PC4-14900	233 MHz	933 MHz	1866 MHz	14.9 GB / s
DDR4-2133	PC4-17000	266 MHz	1066 MHz	2133 MHz	17.0 GB / s
DDR4-2400	PC4-19200	300 MHz	1200 MHz	2400 MHz	19.2 GB / s
DDR4-2666	PC4-21300	333 MHz	1333 MHz	2666 MHz	21.3 GB / s
DDR4-2933	PC4-23466	366 MHz	1466 MHz	2933 MHz	23.5 GB / s
DDR4-3200	PC4-25600	400 MHz	1600 MHz	3200 MHz	25.6 GB / s

Benefits of DDR4 RAM

Compared to its predecessor, the RAM is clocked even higher, which means that higher transfer rates can be achieved. At the same time the voltage is lowered to 1.2 V. Thanks to chip stacking technology, up to eight storage layers can be stacked on top of one another. This not only increases the maximum storage capacity, but also the signal quality of the individual modules. DDR4 also has improved error detection and correction.

DDR5 SDRAM

DDR5 should come onto the market in 2020, there are already first samples. The specification was officially published in July 2020 (downloadable fee).

Specifications

chip	module	Storage cycle	I / O cycle	Effective tact	Transfer rate
					per 64-bit module
DDR5-3200	PC5-25600	200 MHz	01600 MHz	3200 MHz	2 × 12.8 GB / s
DDR5-3600	PC5-28800	225 MHz	01800 MHz	3600 MHz	2 × 14.4 GB / s
DDR5-4000	PC5-32000	250 MHz	2000 MHz	4000 MHz	2 × 16.0 GB / s
...
DDR5-8000	PC5-64000	500 MHz	4000 MHz	8000 MHz	2 × 32.0 GB / s
DDR5-8400	PC5-67200	525 MHz	4200 MHz	8400 MHz	2 × 33.6 GB / s

There are important improvements between DDR4 and DDR5 RAM:

• 16-way and optionally 32-way prefetch, division of the interface into two channels (as with DDR4-LPDIMM and GDDR-6-RAM)
• extensive calibration options for all signal lines
• DFE (Decision Feedback Equalization), with which strongly distorted signals can be restored
• On-Die-ECC, every RAM has 6.25% additional RAM cells inside to detect and correct errors even with non-ECC RAM. This test can be carried out periodically and independently of the CPU.
• Combinations of DRAM, Flash and other persistent memories (NVDIMM-N / F / P)

"Post-DDR5" -SDRAM

The development is currently still at the very beginning. A longer development time of 5 to 6 years with the possibility of new concepts is aimed for. In addition to maintaining the basic principles of the architecture of the current DDR RAM, an approximation of the RAM interface and the PCI Express interface is under discussion. The latter would go in the direction that all communication of a CPU goes via PCI-Express (peripherals, mass storage, CPU-to-CPU communication, volatile memory). Other directions discussed are the integration of the main memory in the CPUs, similar to HBM, and the merging of volatile and persistent memories (as with DDR5 NVDIMM-P).

Calculation of memory transfer rate

The following formula is used to calculate the theoretically maximum possible memory throughput per channel or, in the case of DDR4, per module:

(Takt der internen Logik (in MHz) × Busbreite (in Bit) × Prefetching-Faktor) / (8 Bit/Byte) = Speichertransferrate (in MByte/s)

Sample calculations

• SDR-66 00Z: ( 066 MHz × 64 bit × 01) / 8 = 00.53 GByte / s
• DDR-400 00: (200 MHz × 64 bit × 02) / 8 = 03.2 GByte / s
• DDR2-800 0: (200 MHz × 64 bit × 04) / 8 = 06.4 GByte / s
• DDR3-1600: (200 MHz × 64 bit × 08) / 8 = 12.8 GByte / s
• DDR4-2133: (266 MHz × 64 bit × 08) / 8 = 17.0 GByte / s
• DDR4-2400: (300 MHz × 64 bit × 08) / 8 = 19.2 GByte / s
• DDR5-5200: (325 MHz × 64 bit × 16) / 8 = 41.6 GByte / s

DDR-SDRAM always transfers data with rising and falling clock edges, with DDR2, DDR3 and DDR4 the external clock is increased by a factor of two or four compared to the clock rate of the memory chips, since reads are made from several memory locations one after the other. When using multi-channel storage subsystems, the cumulative data rate and the maximum amount of storage that can be equipped can be multiplied. Latency times increase somewhat with longer internal paths.

This calculation can be used to roughly estimate how well the RAM and the rest of the system fit together. The memory must be fast enough to be able to process the accesses of all bus masters including the CPU, hard disk controllers and graphics cards.

Single-sided / double-sided

A distinction is made between single-sided and double-sided blocks. In the single-sided variant, all modules are on one side; in the double-sided variant, they are distributed on both sides. A common myth is that design has an impact on performance. This is not true, however, because it is not the physical structure but the logical organization that has an influence (more precisely the so-called rank). However, double-sided modules usually have twice as many ranks as comparable single-sided modules, but this does not have to be the case.

"Myth" of the slowness of DDR2-SDRAM compared to DDR1

In connection with DDR2-SDRAM, there was often talk of a disadvantage in the access time compared to DDR-SDRAM modules. But that is only partially correct. In practice, the latency depends on the real clock rate and the access time of the RAM. Since a with 533 MHz resp. 667 MHz specified DDR2 module with a real clock of 133 MHz resp. 166 MHz, it cannot compete with a DDR-400 module in every area. In addition, DDR2 memory is operated almost exclusively with a command rate of 2T, with DDR-400 often 1T is also possible. This also means a strong performance disadvantage. The theoretical maximum data rate of the DDR2 module is higher, but 66 MHz resp. 33 MHz clock, which increases the latency when accessing the RAM, which means that the advantage of the higher data rate is largely lost. Since a DDR2 module sends four data packets per cycle, but not necessarily all of them are used later (the following three are simply read out for the requested packet), the increased data rate cannot be fully used. When the DDR2 memory appeared, the early modules generally had very long access times, which reinforced the myth.

Therefore it makes sense to switch from DDR-400 to DDR2-800 or higher. A DDR2-800 SDRAM can catch up in terms of latency and also deliver theoretically twice the data rate. This is only recommended without reservation if the board can actually process a memory clock of 200 MHz; A dual RAM board (with both DDR and DDR2 slots, of which only one type can be used at a time) has a bottleneck if it can be equipped with DDR-400, but also with DDR2-533; so in such a case DDR-400 (with 200 MHz memory clock) is preferable to the "wider" but slower DDR2 (only 133 MHz memory clock).

It should be especially emphasized that the real clock rates of the SDRAM memory remained constant for a long time. Only with DDR4 is there an increase again.

Latency times in comparison

Latency times of different memory generations

Storage type	Timing values	CL (ns)	tRCD (ns)	tRP (ns)	tRAS (ns)
DDR-266	CL2.5-3-3-6	18.7	22.5	22.5	45.0
DDR-400	CL3-3-2-8	15.0	15.0	15.0	40.0
DDR2-666	CL4-4-4-12	12.0	12.0	12.0	36.0
DDR2-666	CL5-5-5-15	15.0	15.0	15.0	45.0
DDR2-800	CL4-4-4-15	10.0	10.0	10.0	37.5
DDR2-800	CL5-5-5-12	12.5	12.5	12.5	30.0
DDR2-800	CL5-5-5-15	12.5	12.5	12.5	37.5
DDR2-1066	CL4-4-4-12	07.5	07.5	07.5	22.5
DDR2-1066	CL5-5-5-15	09.4	09.4	09.4	28.1
DDR2-1066	CL7-7-7-21	13.1	13.1	13.1	39.4
DDR3-1333	CL7-7-7-21	10.5	10.5	10.5	31.5
DDR3-1333	CL9-9-9-24	13.5	13.5	13.5	36.0
DDR3-1600	CL6-8-6-24	07.5	10.0	07.5	30.0
DDR3-1600	CL11-11-11-28	13.8	13.8	13.8	35.0
DDR3-1866	CL7-7-7-18	07.5	07.5	07.5	19.3
DDR3-1866	CL9-10-9-28	09.6	10.7	09.6	30.0
DDR3-2133	CL9-11-9-28	08.4	10.3	08.4	26.3
DDR3-2933	CL12-14-14-35	08.2	09.5	09.5	23.9
DDR4-2133	CL10-12-12-28	09.4	11.3	11.3	26.3
DDR4-2400	CL11-13-13-31	09.2	10.8	10.8	25.8
DDR4-2933	CL16-18-18-36	10.9	12.3	12.3	24.5
DDR4-4000	CL19-23-23-45	09.5	11.5	11.5	22.5
DDR5-4000	CL30-30-30-64	15.0	15.0	15.0	32.0

The performance of memory modules is measured primarily in the "absolute latency". The absolute latency results from the factors (effective) clock and timing .

Examples

Since the memory bus works with exactly 200 MHz in each of the following three cases, but the timings are based on the effective clock (400 MHz, 800 MHz and 1600 MHz), the latency times (in the range of a few nanoseconds) remain identical, although the timings are identical distinguish. The theoretical data rate doubles due to the fact that the I / O bus works with 200, 400 or 800 MHz:

calculation

As can be seen from the examples just mentioned, the latency can be calculated as follows:

${\displaystyle {\text{Zugriffszeit}}\geqslant {\frac {t_{CL}+t_{RCD}}{\text{Taktfrequenz}}}={\frac {2\cdot (t_{CL}+t_{RCD})}{\text{effektive Taktfrequenz}}}}$

The total access time is at least divided by the clock. The effective clock frequency is twice as high as the actual clock frequency, since it is read twice per clock (hence the name DDR = Double Data Rate ). ${\displaystyle t_{RCD}+t_{CL}}$

Deviations from the specification

Most memory manufacturers offer RAM that does not comply with the official specifications of JEDEC or does not comply with all operating modes. These are stored profiles of the various parameters, including clock rate, timing and operating voltage. Their entirety is u. a. referred to as the Timings Table, for example from the widespread freeware CPU-Z . Above all, it concerns the highest mode as a particularly fast designed bar, i. H. those with higher clock rates and / or better timings. These products are often referred to as "OC-RAM" (memory modules for overclockers). While z. B. DDR3-1600 CL9-9-9 is subject to an official specification, DDR3-1600 CL8-8-8 and DDR4-3466 CL16-18-16 are not JEDEC standards. For future types of main memory, it is to be expected that ever faster memory modules will be offered as a result of the constant improvement in manufacturing processes. However, these will work outside of the official specification, at least initially. JEDEC could include these memory modules in the official specification, but this often only happens years after they are first available. Such modules only work satisfactorily from the start if their parameters are stored correctly (profiles) and these can be adopted by the system. If this is not the case, they are operated in accordance with the standards or adjusted by the mainboard. If neither is possible, the system will refuse to operate.

See also

• Dual channel
• Triple channel
• Quad channel

literature

• Christof Windeck: memory cells. c't 6/2006 p. 278ff; Riegel-Reigen c't 7/2006 p. 238ff; High-speed versus standard. c't 8/2006 p. 210ff - series of articles about the structure and functionality of DDR2 memory modules

Web links

• JEDEC website - the standardization body for storage standards

Individual evidence

1. ↑ ^{a b c} DDR-SDRAM (DDR1 / DDR2 / DDR3) - page in the electronics compendium ; Status: July 3, 2012. Accessed: July 5, 2012
2. ↑ Micron Announces Its First Fully Functional DDR4 DRAM Module ( Memento of the original from May 12, 2012 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. - Reported to Micron , May 7, 2012. Accessed July 3, 2012 
3. ↑ techhive.com TechHive: Adoption of DDR4 memory faces delays (English)
4. ↑ icinsights.com
5. ↑ What's new with DDR4-RAM Article at www.Hardwareschotte.de from August 16, 2014. Accessed on: August 20, 2014
6. ↑ SK Hynix has developed DDR5-5200 - Golem.de. November 15, 2018, accessed April 12, 2019 . 
7. ↑ JEDEC Publishes New DDR5 Standard for Advancing Next-Generation High Performance Computing Systems | JEDEC. Retrieved July 15, 2020 . 
8. ↑ RAM: DDR5 specifications are final - Golem.de. Retrieved on July 15, 2020 (German).