Memory alignment
In the computer architecture ( computer ) a refers to data element (or operands) with n bytes than in the memory aligned ( English Data Alignment , Data Structure padding ), if the address A is an integer multiple of n is ( A mod n = 0). However, if n is not a power of 2, then n must be rounded up to the next higher power of 2 for the calculation . Example: A 5-byte data element must be aligned according to an 8-byte data element.
If the address of a multibyte data element is not such a multiple, it is not aligned ( data misalignment ). A 1-byte data element is always aligned.
The main memory is typically addressed byte by byte , and a sequence of m bytes can be accessed in one cycle. The number m is the width of the data bus in bytes. Usual data bus widths are 16 bits ( m = 2), 32 bits ( m = 4) and 64 bits ( m = 8).
If the operands are aligned in the memory, only one memory access is necessary for n less than or equal to m . Even with n greater than m , only the minimum number of memory accesses is necessary. The disadvantage of the memory alignment is that it may not be possible to use the memory completely. In the above example of the 5-byte data element, three eighths of the memory remain unused.
If the operands in the memory are not aligned, the memory can be used without gaps even with any mix of the data formats . However, depending on the random arrangement, more memory accesses may have to take place than would actually be minimally necessary for such a data element. The operand parts then have to be reassembled again by additional shift operations. (Strictly speaking, if n is greater than m , shift operations are also necessary, but these are unavoidable with a given data bus width and are therefore not a "data misalignment".)
Depending on the processor architecture used, access to non-aligned data is not supported at all on the hardware side. In this case, a special program routine, which composes the data in software, would have to be implemented and executed for each access. The additional effort goes far beyond mere additional memory accesses.
The memory alignment is only discussed in order to minimize the number of memory accesses through automatisms in the arrangement of data elements. The fact that with n = m + 1, regardless of the memory alignment, two memory accesses are always necessary, shows the limits of the rules set out at the beginning. In the example of the 5-byte data element, which has already been used several times, a correct memory alignment could initially be classified as superfluous with a 4-byte data bus width. If, however, porting to a data bus twice as wide takes place later, the omitted memory alignment will require additional effort.
Another special case 2n = 3m could, if it does not coincide with the previous special case, make a half-hearted memory alignment appear appropriate: An exemplary sequence of several 6-byte data elements can be aligned either well, better or poorly with a 4-byte data bus width. It would be good to observe the rules for memory alignment for the first data element and to connect further data elements flush. Two accesses would always be necessary. It would be better to critically question a possible porting to a data bus that is twice as wide and, if necessary, to operate a rule-compliant memory alignment.
In practice, the data was, and it is common to align one step higher than for the target machine necessary to at least a schedule Busbreitenverdopplung: In 8-bit computers have been and are 16-bit values stored as a precaution at even addresses, and in nowadays 64-bit processors are recommended to have 128-bit alignments or compilers adhere to them.
Individual evidence
- ↑ Denise Dudek et al. a .: Network security and protection against hackers. In: TeleMatics Technical Reports. University of Karlsruhe, Institute for Telematics, 2008, accessed on August 9, 2015 .