AMD K10

AMD K10 (also known as "AMD Next Generation Processor Technology" or "Stars") is the code name of a microarchitecture for microprocessors from AMD that has supplemented the K8 and K9 generations and replaced them in the medium term. The K10 microarchitecture is still based on the AMD64 microarchitecture, which has been in use for a long time .

The K10 microarchitecture was previously erroneously referred to as the AMD K8L , but this is the code name of a power-saving variant of the K8 microarchitecture.

Technical

Block diagram of the K10 architecture. The differences between the K8 and K10 architecture are shown in red.

The K10 microarchitecture is designed from the ground up as a multi-core processor .

On a The were up to four cores with their dedicated (i. E. The dedicated) in the production in the 65-nm process cache , up to two memory controller , the crossbar and of all cores shared, 2  MiB large L3 cache housed.

With the conversion of production to 45 nm, up to six cores have now been implemented and the L3 cache has grown to up to 6 MB. At the same time, there are now models without an L3 cache.

45 nm CPUs with the L3 cache perform better in IPC ( Instructions per Cycle ) than their 65 nm ancestors, while CPUs without L3 cache have a smaller IPC on average.

Compared to the K9 , the crossbar had to be expanded in order to address additional cores.

The memory controllers had to be adapted and optimized to the changed cache hierarchy .

Thanks to the shared L3 cache, the cores can normally communicate with one another without going through the relatively slow main memory. A detour is only necessary with these processors if the shared cache is insufficient or the data has already been swapped out to the main memory for other reasons.

A revised floating point unit is intended to greatly increase floating point throughput. Furthermore, advanced power-saving technologies with separate supply lines for the individual processor cores and the memory controller (“split power planes”) as well as a faster HyperTransport connection (version 3.0) are available on newer mainboards. However, the advanced power-saving technologies are only fully developed in the 45 nm models; the 65 nm models could not convince in idle compared to the K9 generation.

Due to the extensive changes to the processor interfaces and the power supply, new processor sockets have been introduced for the K10 generation. For motherboards with one processor, this is the AM2 + socket , or the AM3 socket if you want to use DDR3 as the main memory and it is a newer 45 nm CPU. However, there is still the limited possibility of using the new generation with reduced functionality and possibly performance (e.g. higher power consumption) in the older processor sockets Socket AM2 and Socket F , provided a BIOS update has been provided by the mainboard manufacturer.

Differences to the K8 architecture :

• Extended instruction queue: The instruction queue is used to store commands in advance. Instead of 16 bytes per clock cycle, 32 bytes per clock cycle are now possible.
• Improve branch prediction: Advanced Branch Prediction ( Advanced Branch Prediction ) with now 512 entries and doubling the return stack .
• Sideband Stack Optimizer: This is a new addition and performs stack optimizations for POP / PUSH operations.
• Improving the TLB: The Translation Lookaside Buffer (TLB) now supports 1  GiB large pages . A processor core with K10 architecture now addresses the memory with 48 bits compared to 40 bits for the K8. The addressable memory area is now up to 256  TiB . According to AMD, this should increase the working speed for large databases and virtual environments .
• Introduction of SSE4a or SSE128: two 128-bit SSE commands can be read in per clock cycle and core. This means that up to four floating point operations with double precision are possible per clock cycle. With the K8 architecture, the SSE path is “only” 64 bits wide. There are also new SSE4a commands : EXTRQ, INSERTQ, MOVNTSD, MOVNTSS. The SSE commands for bit manipulation are also expanded: LZCNT, POPCNT.
• Independent memory controller: With an independent memory controller, more DRAM banks are possible, there are fewer page conflicts and larger burst lengths are possible. Write bursting is intended to bundle multiple write and read accesses to the memory and to execute them in one pass. This is intended to increase the effective storage throughput. In contrast to the K8 and K9, the K10 can optionally control the two memory channels independently ("unganged" mode). This means that the CPU can simultaneously read and write to the memory.
• L2 cache: The data connection between the processor core and the L2 cache has been expanded from 128 bits to 256 bits.
• Shared L3 cache: All processor cores can access this shared cache.

Naming

The desktop processors of the K10 generation (AMD Family 10h Processor) are sold under three instead of two brand names. The models with an L3 cache are marketed under the new product name Phenom , those without an L3 cache as the Athlon . In addition, as with the AMD Athlon X2, the designation system is no longer based on the Quantispeed rating, but on a structured type number, similar to the AMD Opteron .

The first Phenom series with four-digit model numbers was presented at the end of November 2007 (at that time still under the name AMD Phenom without the addition X4). At the end of March 2008 the three-core processors with the name Phenom X3 followed , in October 2008 Athlon models based on it.

At the beginning of 2009 the AMD Phenom II and a little later the AMD Athlon II were presented. These have three-digit model numbers and are manufactured in a more modern production process, which significantly reduces power consumption and enables significantly higher clock rates.

In the server area, the successful product name AMD Opteron will be retained. The first products with the quad-core processor “Barcelona” were launched on September 10, 2007.

The first processors with an integrated graphics processor, so-called APUs (AMD Family 12h Processor), also have processor cores based on the K10 architecture. These CPUs / APUs are grouped under the AMD Fusion concept , but do not have any marketing names in the processor name. The APUs are only divided into series such as AMD A4, A6, A8 or A10 series.

K10 microarchitecture processors

The following processor families from AMD are based on the K10 microarchitecture:

• AMD Opteron (K10)
• AMD Phenom II
• AMD Phenom
• AMD Athlon II (only versions for Socket AM2 (+), AM3 and FM1)
• AMD Athlon X2 with Kuma core
• AMD Turion II
• AMD V series
• AMD Sempron (only versions for socket AM3 )
• AMD A8, A6, A4 or E2 series , code name Llano

See also

• List of AMD K10 Processors (Desktop)

Web links

• Software Optimization Guide for AMD Family 10h and 12h Processors (PDF; 1.9 MB)

Individual evidence

1. ↑ ^{a b c d} Simonnet Isaïe - Trouffman: Interview du Nouvel AMD. February 28, 2007, archived from the original on July 12, 2009 ; accessed on January 1, 2014 (English, video interview with Giuseppe Amato (AMD Technical Director: Sales and Marketing EMEA) from February 2007 (no longer available)). 
2. ↑ ^{a b c} AMD: K10 is in the Barcelona . heise online, April 2007.
3. ↑ AMD roadmap until 2008 , computerbase.de
4. ↑ ^{a b c d} AMDs K10: Three-level cache architecture of the Barecelona core presented . April 2007.