AMD Opteron (K10)
| << AMD Opteron | |
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 New AMD Opteron emblem |
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| Production: | since 2007 |
| Producer: | AMD |
| Processor clock: | 1.7 GHz to 3.1 GHz |
| HT cycle: | 1000 MHz to 2400 MHz |
| L3 cache size: | 2 MiB to 16 MiB |
| Instruction set : | x86 / AMD64 |
| Microarchitecture : | AMD K10 / AMD64 |
| Base: | |
Names of the processor cores:
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The AMD Opteron series based on the AMD K10 microarchitecture is a family of 64-bit microprocessors for servers and workstations . These multi-core processors are the successors to the K8 and K9- based AMD Opteron processors.
In general, this processor generation has increased computing power per processor core compared to the K9 generation , which is particularly noticeable in the floating point calculation. In addition, the processors now have a common L3 cache in addition to the four L1 and L2 caches (one per processor core). For details about the architecture and the changes compared to the previous generation, see AMD K10 .
Product history
Barcelona
As the first representative of the K10 generation within the Opteron product family , the Barcelona core, the first native quad-core processor of the x86 world , was launched on September 10, 2007 . Natively, in this context means that the processor from a The consists of four cores, while the main competitor Intel to date only four core processors of two dual-core processors offered, on a carrier were assembled. AMD hoped that this development decision would bring significant speed advantages.
Barcelona is manufactured in 65 nm and with eleven layers of copper SOI and transistors with strained silicon . With a die size of approx. 285 mm² and 463 million transistors, it is a very large core by comparison, which is particularly problematic with regard to the production yield.
Because of the socket F used, Barcelona is suitable for systems with one to two or one to eight processors (23xx and 83xx series) and, according to AMD, it should be possible to use this four-core Opteron in existing double-core Opteron systems, as both the base as well as the TDP remain the same. Initially, these processors are only delivered with a relatively low clock frequency and should only reach the high clock frequencies of the K9 generation (the cores Santa Rosa and Santa Ana ) in the medium term .
Errata
According to AMD, all AMD Opterons of revision BA as well as AMD Phenom of revision B2 have an error in the translation lookaside buffer (TLB) of the L2 cache, which was known in the press as a "TLB bug". This error is said to occur with certain workloads and can only be circumvented by disabling part of the TLB unit or deeply manipulating the software. Deactivating the TLB unit costs at least 10% computing power.
AMD therefore stopped deliveries to large server manufacturers and major customers in December 2007, which amounted to a delivery stop for these processors. The processors were then only available "in the form of labeled processors for certain end-user systems, where customers had the opportunity to get the stability and reliability of the solution going with a BIOS fix or some other workaround using software." A kernel patch was developed by AMD for Linux, which bypasses the problem largely without loss of computing power. The incorrect operations are carried out by software. However, AMD does not generally recommend the patch as it represents a deep intervention in the system.
With the revision B3 the error was corrected and at the beginning of April 2008 AMD was able to deliver Opteron processors in large numbers again.
Shanghai
On November 12, 2008, new processors based on the “Shanghai” core were presented. The differences are essentially production - related changes ( die shrink ) from 65 nm to 45 nm process technology, some detail improvements and an L3 cache that has been enlarged to 6 MiB . Also new is the official support of registered DDR2-SDRAM modules up to PC2-6400R, compared to the PC2-5300R in the predecessor. In addition to an increase in performance, which is often attributed to the larger L3 cache, the power consumption could be significantly reduced.
Istanbul
On February 20, 2009, selected journalists were presented with the further development of Shanghai, called “Istanbul”, with six cores. Like its predecessor, it has a native core design with six arithmetic units and also 6 MiB L3 cache, but also other improvements such as HT Assist , a snoop filter that is intended to reduce the overhead when communicating between several processors. Thus, the Istanbul should benefit more than just from the two additional cores.
Server platform "Fiorano"
At the end of September 2009, AMD presented its own chipsets that also support HT 3.0.
Power consumption
With the Opteron processors based on the K10 architecture, AMD introduced an additional specification for determining the power consumption of the processors. In addition to the Thermal Design Power (TDP), with which AMD continues to indicate the power requirements for which the system must be designed, there is now the Average CPU Power . This is to indicate the typical maximum consumption of a processor. However, both statements are to be published further.
Model numbers
As already introduced with the Opteron of the K9 generation , the Opteron of the K10 generation also have a four-digit model number (see also: OPN ):
- The first number indicates the maximum number of processors of this type that can be used simultaneously on a motherboard (scalability: 1, 2 or up to 8)
- The second digit indicates the processor generation, starting with "3" for the processors of revision Bx. This also ensures that it can be distinguished from the Opteron of the K9 generation , where all processor models have a "2" as the second digit.
- The last two digits encode the processor clock. In general, a larger number here indicates a higher speed.
- If the processor deviates from the standard consumption information, an abbreviation is added which provides information about the electricity requirement .
Examples
- Opteron 8347: Four-core processor of the third generation for systems with four to eight processors, 1900 MHz clock frequency
Model data base G34
All processors for socket G34 have a memory controller for DDR3 SDRAM.
Magny-Cours
Eight- and twelve-core processor
- The Magny-Cours consists of 2 processors based on the Istanbul series (6 cores each) in one housing.
- L1 cache: per core 64 + 64 KiB (data + instructions)
- L2 cache: 512 KiB per core with processor clock
- L3 cache: 8 to 12 MiB
- MMX , Extended 3DNow! , SSE , SSE2 , SSE3 , SSE4a , AMD64 , OPM , NX-Bit , SMP , AMD-V 2.0
- Socket G34 , 4 × HyperTransport 3.0 (HT3)
- Manufacturing technology: 45 nm ( SOI )
- The size: 2 × 346 mm²
- Clock frequencies: 1.7 to 2.5 GHz
- Models: Opteron 6124HE to 6180SE
Interlagos
Eight-, twelve- or sixteen-core processor
- The Interlagos consists of two dies, each with four modules (two cores each) from the Bulldozer series in one housing.
- Manufacturing technology: 32 nm ( SOI )
Model data base F
All processors for socket F have a memory controller with two channels (128 bit, dual-channel operation ) for DDR2-SDRAM ( registered modules required).
Barcelona
- Revisions: BA, B3
- L1 cache: per core 64 + 64 KiB (data + instructions)
- L2 cache: 512 KiB per core with processor clock
- L3 cache: 2048 KiB with northbridge clock
- MMX , Extended 3DNow! , SSE , SSE2 , SSE3 , SSE4a , AMD64 , OPM , NX-Bit , SMP , AMD-V
- Socket F , HyperTransport with 1,000 MHz (HT2000)
- Manufacturing technology: 65 nm ( SOI )
- The size: 285 mm² with 463 million transistors
- Clock frequencies: 1.7-2.5 GHz
- Models: Opteron x344 to x360
Shanghai
- Revision: C2
- L1 cache: per core 64 + 64 KiB (data + instructions)
- L2 cache: 512 KiB per core with processor clock
- L3 cache: 6144 KiB with northbridge clock
- MMX , Extended 3DNow! , SSE , SSE2 , SSE3 , SSE4a , AMD64 , OPM , NX-Bit , SMP , AMD-V
- Socket F , HyperTransport with 1,000 MHz (HT2000)
- Manufacturing technology: 45 nm ( SOI )
- The size: 258 mm² with 758 million transistors
- Clock frequencies: 2.1-3.1 GHz
- Models: Opteron x372 to x393
Istanbul
Six-core processor (Hexa-Core)
- Revision: D0
- L1 cache: per core 64 + 64 KiB (data + instructions)
- L2 cache: 512 KiB per core with processor clock
- L3 cache: 6144 KiB with northbridge clock
- MMX , Extended 3DNow! , SSE , SSE2 , SSE3 , SSE4a , AMD64 , OPM , NX-Bit , SMP , AMD-V
- Socket F , HyperTransport with 1,000 MHz (HT2000)
- Manufacturing technology: 45 nm ( SOI )
- The size: 346 mm² with 904 million transistors
- Clock frequencies: 1.8-2.8 GHz
- Models: Opteron 2419EE to 8439SE
Model data socket AM2 + / AM3
Budapest
- Revisions: B3
- L1 cache: per core 64 + 64 KiB (data + instructions)
- L2 cache: 512 KiB per core with processor clock
- L3 cache: 2048 KiB with northbridge clock
- MMX , Extended 3DNow! , SSE , SSE2 , SSE3 , SSE4a , AMD64 , OPM , NX-Bit , SMP , AMD-V
- Socket AM2 + , HyperTransport with 1,800 MHz (HT3600)
- Manufacturing technology: 65 nm ( SOI )
- The size: 285 mm² with 463 million transistors
- Clock frequencies: 2.1-2.3 GHz
- Models: Opteron 1352 to 1356
Suzuka
- Revisions: C2
- L1 cache: per core 64 + 64 KiB (data + instructions)
- L2 cache: 512 KiB per core with processor clock
- L3 cache: 6144 KiB with northbridge clock
- Support for DDR3 SDRAM
- MMX , Extended 3DNow! , SSE , SSE2 , SSE3 , SSE4a , AMD64 , OPM , NX-Bit , SMP , AMD-V
- Socket AM3 , HyperTransport with 2,200 MHz
- Manufacturing technology: 45 nm ( SOI )
- The size: 258 mm² with 758 million transistors
- Clock frequencies: 2.5-2.9 GHz
- Models: Opteron 1381 to 1389
See also
Individual evidence
- ↑ AMD delays delivery from Barcelona due to TLB bug. In: golem.de , December 2007.
- ↑ Linux patch that bypasses the TLB bug. In: heise.de
- ↑ Press release from AMD
- ↑ AMD puts on the ritz with six-core Opteron demo. In: Techreport.com , report on the presentation of the Istanbul core, February 20, 2009 (English)
- ↑ AMD brings new server chipsets. In: heise.de , September 21, 2009
- ↑ AMD introduces the first four-core processors. In: ComputerBase.de , September 10, 2007
- ↑ Tracy Carver: “Magny-Cours” and Direct Connect Architecture 2.0. (No longer available online.) AMD, March 29, 2010, archived from the original on August 27, 2011 ; Retrieved October 21, 2011 . Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice.
