Bus snooping

from Wikipedia, the free encyclopedia

Bus snooping ( English , sniff ' in a computer system) refers to the continuous control of the memory address lines ( "bus") for eventual conflicts between memory and cache content submissions.


In a multiprocessor system , each processor has its own independent cache . If a subscriber on the host bus changes data in the main memory , this can lead to cache inconsistencies , since the cache line does not contain the modified value of the main memory.

Basic principle

The basic principle of bus snooping is that every participant on the host bus reads the addresses of another participant on the bus and checks its cache to see whether a cache line with the corresponding address is available. For this purpose, the cache controller is expanded to include snoop logic. As a rule, all participants are in this snooping state, with the exception of the participant who carries out the transaction on the bus.

Snoop hit on a write

A participant on the host bus, for example a DMA controller, carries out a write transaction on the bus and creates an address on the bus for this purpose. The other participants who are in the snooping state check whether one of their cache lines is available for the address created. If this is the case, i.e. a so-called hit occurs, it is referred to as a "Snoop Write Hit". In order to avoid an inconsistency of the cache, the cacheline is marked as invalid.

Snoop hit on a read

A participant carries out a read transaction on the host bus and creates the address of the memory area on the bus. The other participants are in the snooping state and read the created address. If a cache line matches the created address, i.e. there is a hit in the cache, it is referred to as a snoop read hit. In this case, read access is interrupted by the listening participant, who writes the changed data into the main memory.

See also


  • James R. Goodman: Using cache memory to reduce processor-memory traffic . In: Proceedings of the 12th International Symposium on Computer Architecture . 1983, p. 124-131 ( PDF ).